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hdl.dsl: further clarify error message for incorrect nesting.

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Fixes #133.
This commit is contained in:
whitequark 2019-07-07 01:03:59 +00:00
parent cb8be4a1b0
commit da1f58b7ae
2 changed files with 12 additions and 4 deletions
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6
nmigen/test/test_hdl_dsl.py
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@ -345,7 +345,8 @@ class DSLTestCase(FHDLTestCase):
m = Module()
with m.Switch(self.s1):
with self.assertRaises(SyntaxError,
msg="If is not permitted directly inside of Switch"):
msg="If is not permitted directly inside of Switch; "
"it is permitted inside of Switch Case"):
with m.If(self.s2):
pass
@ -486,7 +487,8 @@ class DSLTestCase(FHDLTestCase):
with m.State("FOO"):
pass
with self.assertRaises(SyntaxError,
msg="If is not permitted directly inside of FSM"):
msg="If is not permitted directly inside of FSM; "
"it is permitted inside of FSM State"):
with m.If(self.s2):
pass