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hdl.dsl: further clarify error message for incorrect nesting.

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Fixes #133.
This commit is contained in:
whitequark 2019-07-07 01:03:59 +00:00
parent cb8be4a1b0
commit da1f58b7ae
2 changed files with 12 additions and 4 deletions
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10
nmigen/hdl/dsl.py
View file

@ -133,8 +133,14 @@ class Module(_ModuleBuilderRoot, Elaboratable):
raise SyntaxError("{} is not permitted outside of {}" raise SyntaxError("{} is not permitted outside of {}"
.format(construct, context)) .format(construct, context))
else: else:
raise SyntaxError("{} is not permitted directly inside of {}" if self._ctrl_context == "Switch":
.format(construct, self._ctrl_context)) secondary_context = "Case"
if self._ctrl_context == "FSM":
secondary_context = "State"
raise SyntaxError("{} is not permitted directly inside of {}; it is permitted "
"inside of {} {}"
.format(construct, self._ctrl_context,
self._ctrl_context, secondary_context))
def _get_ctrl(self, name): def _get_ctrl(self, name):
if self._ctrl_stack: if self._ctrl_stack:

6
nmigen/test/test_hdl_dsl.py
View file

@ -345,7 +345,8 @@ class DSLTestCase(FHDLTestCase):
m = Module() m = Module()
with m.Switch(self.s1): with m.Switch(self.s1):
with self.assertRaises(SyntaxError, with self.assertRaises(SyntaxError,
msg="If is not permitted directly inside of Switch"): msg="If is not permitted directly inside of Switch; "
"it is permitted inside of Switch Case"):
with m.If(self.s2): with m.If(self.s2):
pass pass
@ -486,7 +487,8 @@ class DSLTestCase(FHDLTestCase):
with m.State("FOO"): with m.State("FOO"):
pass pass
with self.assertRaises(SyntaxError, with self.assertRaises(SyntaxError,
msg="If is not permitted directly inside of FSM"): msg="If is not permitted directly inside of FSM; "
"it is permitted inside of FSM State"):
with m.If(self.s2): with m.If(self.s2):
pass pass