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Consistently use {!r}, not '{!r}' in diagnostics.

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This can cause confusion:
  * If the erroneous object is None, it is printed as 'None', which
    appears as a string (and could be the result of converting None
    to a string.)
  * If the erroneous object is a string, it is printed as ''<val>'',
    which is a rather strange combination of quotes.
This commit is contained in:
whitequark 2019-10-11 11:47:42 +00:00
parent fa1e466a65
commit db960e7c30
16 changed files with 61 additions and 61 deletions
Download patch file Download diff file Expand all files Collapse all files

20
nmigen/test/test_hdl_ast.py
View file

@ -105,9 +105,9 @@ class ConstTestCase(FHDLTestCase):
self.assertEqual(Const(1, (4, True)).shape(), (4, True))
self.assertEqual(Const(0, (0, False)).shape(), (0, False))
def test_shape_bad(self):
def test_shape_wrong(self):
with self.assertRaises(TypeError,
msg="Width must be a non-negative integer, not '-1'"):
msg="Width must be a non-negative integer, not -1"):
Const(1, -1)
def test_normalization(self):
@ -392,10 +392,10 @@ class SliceTestCase(FHDLTestCase):
def test_start_end_wrong(self):
with self.assertRaises(TypeError,
msg="Slice start must be an integer, not ''x''"):
msg="Slice start must be an integer, not 'x'"):
Slice(0, "x", 1)
with self.assertRaises(TypeError,
msg="Slice end must be an integer, not ''x''"):
msg="Slice end must be an integer, not 'x'"):
Slice(0, 1, "x")
def test_start_end_out_of_range(self):
@ -430,7 +430,7 @@ class BitSelectTestCase(FHDLTestCase):
s1 = self.c.bit_select(self.s, 2)
self.assertEqual(s1.stride, 1)
def test_width_bad(self):
def test_width_wrong(self):
with self.assertRaises(TypeError):
self.c.bit_select(self.s, -1)
@ -452,7 +452,7 @@ class WordSelectTestCase(FHDLTestCase):
s1 = self.c.word_select(self.s, 2)
self.assertEqual(s1.stride, 2)
def test_width_bad(self):
def test_width_wrong(self):
with self.assertRaises(TypeError):
self.c.word_select(self.s, 0)
with self.assertRaises(TypeError):
@ -595,9 +595,9 @@ class SignalTestCase(FHDLTestCase):
d10 = Signal(max=1)
self.assertEqual(d10.shape(), (0, False))
def test_shape_bad(self):
def test_shape_wrong(self):
with self.assertRaises(TypeError,
msg="Width must be a non-negative integer, not '-10'"):
msg="Width must be a non-negative integer, not -10"):
Signal(-10)
def test_min_max_deprecated(self):
@ -688,7 +688,7 @@ class ClockSignalTestCase(FHDLTestCase):
self.assertEqual(s2.domain, "pix")
with self.assertRaises(TypeError,
msg="Clock domain name must be a string, not '1'"):
msg="Clock domain name must be a string, not 1"):
ClockSignal(1)
def test_shape(self):
@ -712,7 +712,7 @@ class ResetSignalTestCase(FHDLTestCase):
self.assertEqual(s2.domain, "pix")
with self.assertRaises(TypeError,
msg="Clock domain name must be a string, not '1'"):
msg="Clock domain name must be a string, not 1"):
ResetSignal(1)
def test_shape(self):

4
nmigen/test/test_hdl_dsl.py
View file

@ -625,10 +625,10 @@ class DSLTestCase(FHDLTestCase):
def test_submodule_wrong(self):
m = Module()
with self.assertRaises(TypeError,
msg="Trying to add '1', which does not implement .elaborate(), as a submodule"):
msg="Trying to add 1, which does not implement .elaborate(), as a submodule"):
m.submodules.foo = 1
with self.assertRaises(TypeError,
msg="Trying to add '1', which does not implement .elaborate(), as a submodule"):
msg="Trying to add 1, which does not implement .elaborate(), as a submodule"):
m.submodules += 1
def test_submodule_named_conflict(self):

4
nmigen/test/test_hdl_ir.py
View file

@ -15,13 +15,13 @@ class BadElaboratable(Elaboratable):
class FragmentGetTestCase(FHDLTestCase):
def test_get_wrong(self):
with self.assertRaises(AttributeError,
msg="Object 'None' cannot be elaborated"):
msg="Object None cannot be elaborated"):
Fragment.get(None, platform=None)
with self.assertWarns(UserWarning,
msg=".elaborate() returned None; missing return statement?"):
with self.assertRaises(AttributeError,
msg="Object 'None' cannot be elaborated"):
msg="Object None cannot be elaborated"):
Fragment.get(BadElaboratable(), platform=None)

6
nmigen/test/test_hdl_mem.py
View file

@ -19,10 +19,10 @@ class MemoryTestCase(FHDLTestCase):
def test_geometry_wrong(self):
with self.assertRaises(TypeError,
msg="Memory width must be a non-negative integer, not '-1'"):
msg="Memory width must be a non-negative integer, not -1"):
m = Memory(width=-1, depth=4)
with self.assertRaises(TypeError,
msg="Memory depth must be a non-negative integer, not '-1'"):
msg="Memory depth must be a non-negative integer, not -1"):
m = Memory(width=8, depth=-1)
def test_init(self):
@ -101,7 +101,7 @@ class MemoryTestCase(FHDLTestCase):
def test_write_port_granularity_wrong(self):
mem = Memory(width=8, depth=4)
with self.assertRaises(TypeError,
msg="Write port granularity must be a non-negative integer, not '-1'"):
msg="Write port granularity must be a non-negative integer, not -1"):
mem.write_port(granularity=-1)
with self.assertRaises(ValueError,
msg="Write port granularity must not be greater than memory width (10 > 8)"):

4
nmigen/test/test_lib_cdc.py
View file

@ -7,7 +7,7 @@ from ..lib.cdc import *
class FFSynchronizerTestCase(FHDLTestCase):
def test_stages_wrong(self):
with self.assertRaises(TypeError,
msg="Synchronization stage count must be a positive integer, not '0'"):
msg="Synchronization stage count must be a positive integer, not 0"):
FFSynchronizer(Signal(), Signal(), stages=0)
with self.assertRaises(ValueError,
msg="Synchronization stage count may not safely be less than 2"):
@ -53,7 +53,7 @@ class FFSynchronizerTestCase(FHDLTestCase):
class ResetSynchronizerTestCase(FHDLTestCase):
def test_stages_wrong(self):
with self.assertRaises(TypeError,
msg="Synchronization stage count must be a positive integer, not '0'"):
msg="Synchronization stage count must be a positive integer, not 0"):
ResetSynchronizer(Signal(), stages=0)
with self.assertRaises(ValueError,
msg="Synchronization stage count may not safely be less than 2"):

4
nmigen/test/test_lib_fifo.py
View file

@ -8,10 +8,10 @@ from ..lib.fifo import *
class FIFOTestCase(FHDLTestCase):
def test_depth_wrong(self):
with self.assertRaises(TypeError,
msg="FIFO width must be a non-negative integer, not '-1'"):
msg="FIFO width must be a non-negative integer, not -1"):
FIFOInterface(width=-1, depth=8, fwft=True)
with self.assertRaises(TypeError,
msg="FIFO depth must be a non-negative integer, not '-1'"):
msg="FIFO depth must be a non-negative integer, not -1"):
FIFOInterface(width=8, depth=-1, fwft=True)
def test_sync_depth(self):

8
nmigen/test/test_sim.py
View file

@ -426,7 +426,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
def test_add_process_wrong(self):
with self.assertSimulation(Module()) as sim:
with self.assertRaises(TypeError,
msg="Cannot add a process '1' because it is not a generator or "
msg="Cannot add a process 1 because it is not a generator or "
"a generator function"):
sim.add_process(1)
@ -458,7 +458,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
with self.assertSimulation(self.m) as sim:
def process():
with self.assertRaisesRegex(ValueError,
regex=r"Process '.+?' sent a request to set signal '\(sig s\)', "
regex=r"Process .+? sent a request to set signal \(sig s\), "
r"which is not a part of simulation"):
yield self.s.eq(0)
yield Delay()
@ -469,7 +469,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
with self.assertSimulation(self.m) as sim:
def process():
with self.assertRaisesRegex(ValueError,
regex=r"Process '.+?' sent a request to set signal '\(sig o\)', "
regex=r"Process .+? sent a request to set signal \(sig o\), "
r"which is a part of combinatorial assignment in simulation"):
yield self.o.eq(0)
yield Delay()
@ -479,7 +479,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
with self.assertSimulation(Module()) as sim:
def process():
with self.assertRaisesRegex(TypeError,
regex=r"Received unsupported command '1' from process '.+?'"):
regex=r"Received unsupported command 1 from process .+?"):
yield 1
yield Delay()
sim.add_process(process)