fhdl.ast: add tests for most logic.
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whitequark
parent
e45e7f1608
commit
dc486ad8b9
4 changed files with 391 additions and 50 deletions
0
nmigen/test/__init__.py
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nmigen/test/__init__.py
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358
nmigen/test/test_fhdl.py
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358
nmigen/test/test_fhdl.py
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import unittest
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from nmigen.fhdl.ast import *
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class ValueTestCase(unittest.TestCase):
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def test_wrap(self):
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self.assertIsInstance(Value.wrap(0), Const)
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self.assertIsInstance(Value.wrap(True), Const)
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c = Const(0)
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self.assertIs(Value.wrap(c), c)
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with self.assertRaises(TypeError):
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Value.wrap("str")
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def test_bool(self):
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with self.assertRaises(TypeError):
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if Const(0):
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pass
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def test_len(self):
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self.assertEqual(len(Const(10)), 4)
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def test_getitem_int(self):
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s1 = Const(10)[0]
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self.assertIsInstance(s1, Slice)
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self.assertEqual(s1.start, 0)
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self.assertEqual(s1.end, 1)
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s2 = Const(10)[-1]
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self.assertIsInstance(s2, Slice)
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self.assertEqual(s2.start, 3)
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self.assertEqual(s2.end, 4)
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with self.assertRaises(IndexError):
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Const(10)[5]
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def test_getitem_slice(self):
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s1 = Const(10)[1:3]
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self.assertIsInstance(s1, Slice)
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self.assertEqual(s1.start, 1)
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self.assertEqual(s1.end, 3)
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s2 = Const(10)[1:-2]
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self.assertIsInstance(s2, Slice)
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self.assertEqual(s2.start, 1)
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self.assertEqual(s2.end, 2)
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s3 = Const(31)[::2]
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self.assertIsInstance(s3, Cat)
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self.assertIsInstance(s3.operands[0], Slice)
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self.assertEqual(s3.operands[0].start, 0)
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self.assertEqual(s3.operands[0].end, 1)
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self.assertIsInstance(s3.operands[1], Slice)
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self.assertEqual(s3.operands[1].start, 2)
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self.assertEqual(s3.operands[1].end, 3)
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self.assertIsInstance(s3.operands[2], Slice)
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self.assertEqual(s3.operands[2].start, 4)
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self.assertEqual(s3.operands[2].end, 5)
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def test_getitem_wrong(self):
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with self.assertRaises(TypeError):
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Const(31)["str"]
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class ConstTestCase(unittest.TestCase):
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def test_bits_sign(self):
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self.assertEqual(Const(0).bits_sign(), (0, False))
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self.assertEqual(Const(1).bits_sign(), (1, False))
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self.assertEqual(Const(10).bits_sign(), (4, False))
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self.assertEqual(Const(-10).bits_sign(), (4, True))
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self.assertEqual(Const(1, 4).bits_sign(), (4, False))
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self.assertEqual(Const(1, (4, True)).bits_sign(), (4, True))
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with self.assertRaises(TypeError):
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Const(1, -1)
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def test_value(self):
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self.assertEqual(Const(10).value, 10)
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def test_repr(self):
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self.assertEqual(repr(Const(10)), "(const 4'd10)")
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self.assertEqual(repr(Const(-10)), "(const 4'sd-10)")
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def test_hash(self):
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with self.assertRaises(TypeError):
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hash(Const(0))
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class OperatorTestCase(unittest.TestCase):
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def test_invert(self):
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v = ~Const(0, 4)
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self.assertEqual(repr(v), "(~ (const 4'd0))")
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self.assertEqual(v.bits_sign(), (4, False))
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def test_neg(self):
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v1 = -Const(0, (4, False))
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self.assertEqual(repr(v1), "(- (const 4'd0))")
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self.assertEqual(v1.bits_sign(), (5, True))
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v2 = -Const(0, (4, True))
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self.assertEqual(repr(v2), "(- (const 4'sd0))")
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self.assertEqual(v2.bits_sign(), (4, True))
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def test_add(self):
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v1 = Const(0, (4, False)) + Const(0, (6, False))
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self.assertEqual(repr(v1), "(+ (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (7, False))
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v2 = Const(0, (4, True)) + Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (7, True))
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v3 = Const(0, (4, True)) + Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (6, True))
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v4 = Const(0, (4, False)) + Const(0, (4, True))
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self.assertEqual(v4.bits_sign(), (6, True))
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v5 = 10 + Const(0, 4)
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self.assertEqual(v5.bits_sign(), (5, False))
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def test_sub(self):
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v1 = Const(0, (4, False)) - Const(0, (6, False))
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self.assertEqual(repr(v1), "(- (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (7, False))
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v2 = Const(0, (4, True)) - Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (7, True))
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v3 = Const(0, (4, True)) - Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (6, True))
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v4 = Const(0, (4, False)) - Const(0, (4, True))
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self.assertEqual(v4.bits_sign(), (6, True))
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v5 = 10 - Const(0, 4)
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self.assertEqual(v5.bits_sign(), (5, False))
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def test_mul(self):
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v1 = Const(0, (4, False)) * Const(0, (6, False))
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self.assertEqual(repr(v1), "(* (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (10, False))
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v2 = Const(0, (4, True)) * Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (9, True))
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v3 = Const(0, (4, True)) * Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (8, True))
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v5 = 10 * Const(0, 4)
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self.assertEqual(v5.bits_sign(), (8, False))
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def test_and(self):
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v1 = Const(0, (4, False)) & Const(0, (6, False))
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self.assertEqual(repr(v1), "(& (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (6, False))
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v2 = Const(0, (4, True)) & Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (6, True))
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v3 = Const(0, (4, True)) & Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (5, True))
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v4 = Const(0, (4, False)) & Const(0, (4, True))
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self.assertEqual(v4.bits_sign(), (5, True))
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v5 = 10 & Const(0, 4)
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self.assertEqual(v5.bits_sign(), (4, False))
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def test_or(self):
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v1 = Const(0, (4, False)) | Const(0, (6, False))
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self.assertEqual(repr(v1), "(| (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (6, False))
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v2 = Const(0, (4, True)) | Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (6, True))
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v3 = Const(0, (4, True)) | Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (5, True))
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v4 = Const(0, (4, False)) | Const(0, (4, True))
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self.assertEqual(v4.bits_sign(), (5, True))
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v5 = 10 | Const(0, 4)
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self.assertEqual(v5.bits_sign(), (4, False))
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def test_xor(self):
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v1 = Const(0, (4, False)) ^ Const(0, (6, False))
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self.assertEqual(repr(v1), "(^ (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (6, False))
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v2 = Const(0, (4, True)) ^ Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (6, True))
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v3 = Const(0, (4, True)) ^ Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (5, True))
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v4 = Const(0, (4, False)) ^ Const(0, (4, True))
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self.assertEqual(v4.bits_sign(), (5, True))
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v5 = 10 ^ Const(0, 4)
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self.assertEqual(v5.bits_sign(), (4, False))
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def test_lt(self):
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v = Const(0, 4) < Const(0, 6)
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self.assertEqual(repr(v), "(< (const 4'd0) (const 6'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_le(self):
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v = Const(0, 4) <= Const(0, 6)
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self.assertEqual(repr(v), "(<= (const 4'd0) (const 6'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_gt(self):
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v = Const(0, 4) > Const(0, 6)
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self.assertEqual(repr(v), "(> (const 4'd0) (const 6'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_ge(self):
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v = Const(0, 4) >= Const(0, 6)
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self.assertEqual(repr(v), "(>= (const 4'd0) (const 6'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_eq(self):
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v = Const(0, 4) == Const(0, 6)
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self.assertEqual(repr(v), "(== (const 4'd0) (const 6'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_ne(self):
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v = Const(0, 4) != Const(0, 6)
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self.assertEqual(repr(v), "(!= (const 4'd0) (const 6'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_mux(self):
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s = Const(0)
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v1 = Mux(s, Const(0, (4, False)), Const(0, (6, False)))
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self.assertEqual(repr(v1), "(m (const 0'd0) (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (6, False))
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v2 = Mux(s, Const(0, (4, True)), Const(0, (6, True)))
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self.assertEqual(v2.bits_sign(), (6, True))
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v3 = Mux(s, Const(0, (4, True)), Const(0, (4, False)))
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self.assertEqual(v3.bits_sign(), (5, True))
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v4 = Mux(s, Const(0, (4, False)), Const(0, (4, True)))
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self.assertEqual(v4.bits_sign(), (5, True))
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def test_bool(self):
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v = Const(0).bool()
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self.assertEqual(repr(v), "(b (const 0'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_hash(self):
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with self.assertRaises(TypeError):
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hash(Const(0) + Const(0))
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class SliceTestCase(unittest.TestCase):
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def test_bits_sign(self):
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s1 = Const(10)[2]
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self.assertEqual(s1.bits_sign(), (1, False))
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s2 = Const(-10)[0:2]
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self.assertEqual(s2.bits_sign(), (2, False))
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def test_repr(self):
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s1 = Const(10)[2]
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self.assertEqual(repr(s1), "(slice (const 4'd10) 2:3)")
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class CatTestCase(unittest.TestCase):
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def test_bits_sign(self):
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c1 = Cat(Const(10))
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self.assertEqual(c1.bits_sign(), (4, False))
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c2 = Cat(Const(10), Const(1))
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self.assertEqual(c2.bits_sign(), (5, False))
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c3 = Cat(Const(10), Const(1), Const(0))
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self.assertEqual(c3.bits_sign(), (5, False))
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def test_repr(self):
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c1 = Cat(Const(10), Const(1))
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self.assertEqual(repr(c1), "(cat (const 4'd10) (const 1'd1))")
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class ReplTestCase(unittest.TestCase):
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def test_bits_sign(self):
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r1 = Repl(Const(10), 3)
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self.assertEqual(r1.bits_sign(), (12, False))
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def test_count_wrong(self):
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with self.assertRaises(TypeError):
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Repl(Const(10), -1)
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with self.assertRaises(TypeError):
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Repl(Const(10), "str")
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def test_repr(self):
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r1 = Repl(Const(10), 3)
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self.assertEqual(repr(r1), "(repl (const 4'd10) 3)")
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class SignalTestCase(unittest.TestCase):
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def test_bits_sign(self):
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s1 = Signal()
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self.assertEqual(s1.bits_sign(), (1, False))
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s2 = Signal(2)
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self.assertEqual(s2.bits_sign(), (2, False))
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s3 = Signal((2, False))
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self.assertEqual(s3.bits_sign(), (2, False))
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s4 = Signal((2, True))
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self.assertEqual(s4.bits_sign(), (2, True))
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s5 = Signal(max=16)
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self.assertEqual(s5.bits_sign(), (4, False))
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s6 = Signal(min=4, max=16)
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self.assertEqual(s6.bits_sign(), (4, False))
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s7 = Signal(min=-4, max=16)
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self.assertEqual(s7.bits_sign(), (5, True))
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s8 = Signal(min=-20, max=16)
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self.assertEqual(s8.bits_sign(), (6, True))
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with self.assertRaises(ValueError):
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Signal(min=10, max=4)
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with self.assertRaises(ValueError):
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Signal(2, min=10)
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with self.assertRaises(TypeError):
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Signal(-10)
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def test_name(self):
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s1 = Signal()
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self.assertEqual(s1.name, "s1")
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s2 = Signal(name="sig")
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self.assertEqual(s2.name, "sig")
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def test_reset(self):
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s1 = Signal(4, reset=0b111, reset_less=True)
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self.assertEqual(s1.reset, 0b111)
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self.assertEqual(s1.reset_less, True)
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def test_attrs(self):
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s1 = Signal()
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self.assertEqual(s1.attrs, {})
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s2 = Signal(attrs={"no_retiming": True})
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self.assertEqual(s2.attrs, {"no_retiming": True})
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def test_repr(self):
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s1 = Signal()
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self.assertEqual(repr(s1), "(sig s1)")
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def test_like(self):
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s1 = Signal.like(Signal(4))
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self.assertEqual(s1.bits_sign(), (4, False))
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s2 = Signal.like(Signal(min=-15))
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self.assertEqual(s2.bits_sign(), (5, True))
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s3 = Signal.like(Signal(4, reset=0b111, reset_less=True))
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self.assertEqual(s3.reset, 0b111)
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self.assertEqual(s3.reset_less, True)
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s4 = Signal.like(Signal(attrs={"no_retiming": True}))
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self.assertEqual(s4.attrs, {"no_retiming": True})
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s5 = Signal.like(10)
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self.assertEqual(s5.bits_sign(), (4, False))
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class ClockSignalTestCase(unittest.TestCase):
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def test_domain(self):
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s1 = ClockSignal()
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self.assertEqual(s1.domain, "sync")
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s2 = ClockSignal("pix")
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self.assertEqual(s2.domain, "pix")
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with self.assertRaises(TypeError):
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ClockSignal(1)
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def test_repr(self):
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s1 = ClockSignal()
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self.assertEqual(repr(s1), "(clk sync)")
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class ResetSignalTestCase(unittest.TestCase):
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def test_domain(self):
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s1 = ResetSignal()
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self.assertEqual(s1.domain, "sync")
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s2 = ResetSignal("pix")
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self.assertEqual(s2.domain, "pix")
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with self.assertRaises(TypeError):
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ResetSignal(1)
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def test_repr(self):
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s1 = ResetSignal()
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self.assertEqual(repr(s1), "(reset sync)")
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