fhdl.ast: add tests for most logic.
This commit is contained in:
whitequark
parent
e45e7f1608
commit
dc486ad8b9
0
nmigen/__init__.py
Normal file
0
nmigen/__init__.py
Normal file
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@ -36,17 +36,6 @@ class Value:
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.format(repr(obj), type(obj)))
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def __bool__(self):
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# Special case: Consts and Signals are part of a set or used as
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# dictionary keys, and Python needs to check for equality.
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if isinstance(self, Operator) and self.op == "==":
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a, b = self.operands
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if isinstance(a, Const) and isinstance(b, Const):
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return a.value == b.value
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if isinstance(a, Signal) and isinstance(b, Signal):
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return a is b
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if (isinstance(a, Const) and isinstance(b, Signal)
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or isinstance(a, Signal) and isinstance(b, Const)):
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return False
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raise TypeError("Attempted to convert Migen value to boolean")
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def __invert__(self):
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@ -187,13 +176,13 @@ class Value:
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>>> Value.bits_sign(C(0xaa))
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8, False
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"""
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raise TypeError("Cannot calculate bit length of {!r}".format(self))
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raise NotImplementedError # :nocov:
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def _lhs_signals(self):
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raise TypeError("Value {!r} cannot be used in assignments".format(self))
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def _rhs_signals(self):
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raise NotImplementedError
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raise NotImplementedError # :nocov:
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def __hash__(self):
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raise TypeError("Unhashable type: {}".format(type(self).__name__))
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@ -232,12 +221,6 @@ class Const(Value):
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def _rhs_signals(self):
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return ValueSet()
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def __eq__(self, other):
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return self.value == other.value
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def __hash__(self):
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return hash(self.value)
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def __repr__(self):
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return "(const {}'{}d{})".format(self.nbits, "s" if self.signed else "", self.value)
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@ -301,23 +284,20 @@ class Operator(Value):
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elif self.op == "&" or self.op == "^" or self.op == "|":
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return self._bitwise_binary_bits_sign(*obs)
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elif (self.op == "<" or self.op == "<=" or self.op == "==" or self.op == "!=" or
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self.op == ">" or self.op == ">="):
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self.op == ">" or self.op == ">=" or self.op == "b"):
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return 1, False
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elif self.op == "~":
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return obs[0]
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elif self.op == "m":
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return _bitwise_binary_bits_sign(obs[1], obs[2])
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return self._bitwise_binary_bits_sign(obs[1], obs[2])
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else:
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raise TypeError
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raise TypeError # :nocov:
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def _rhs_signals(self):
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return union(op._rhs_signals() for op in self.operands)
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def __repr__(self):
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if len(self.operands) == 1:
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return "({} {})".format(self.op, self.operands[0])
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elif len(self.operands) == 2:
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return "({} {} {})".format(self.op, self.operands[0], self.operands[1])
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return "({} {})".format(self.op, " ".join(map(repr, self.operands)))
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def Mux(sel, val1, val0):
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@ -470,7 +450,10 @@ class Repl(Value):
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return len(self.value) * self.count, False
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def _rhs_signals(self):
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return value._rhs_signals()
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return self.value._rhs_signals()
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def __repr__(self):
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return "(repl {!r} {})".format(self.value, self.count)
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class Signal(Value, DUID):
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@ -538,18 +521,18 @@ class Signal(Value, DUID):
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self.signed = min < 0 or max < 0
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self.nbits = builtins.max(bits_for(min, self.signed), bits_for(max, self.signed))
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elif isinstance(bits_sign, int):
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if not (min is None or max is None):
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else:
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if not (min is None and max is None):
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raise ValueError("Only one of bits/signedness or bounds may be specified")
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if isinstance(bits_sign, int):
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self.nbits, self.signed = bits_sign, False
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else:
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self.nbits, self.signed = bits_sign
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if not isinstance(self.nbits, int) or self.nbits < 0:
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raise TypeError("Width must be a positive integer, not {!r}".format(self.nbits))
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self.reset = reset
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self.reset_less = reset_less
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self.reset = int(reset)
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self.reset_less = bool(reset_less)
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self.attrs = OrderedDict(() if attrs is None else attrs)
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@ -564,7 +547,7 @@ class Signal(Value, DUID):
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"""
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kw = dict(bits_sign=cls.wrap(other).bits_sign())
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if isinstance(other, cls):
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kw.update(reset=other.reset.value, reset_less=other.reset_less, attrs=other.attrs)
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kw.update(reset=other.reset, reset_less=other.reset_less, attrs=other.attrs)
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kw.update(kwargs)
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return cls(**kw)
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@ -589,17 +572,17 @@ class ClockSignal(Value):
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Parameters
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----------
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cd : str
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Clock domain to obtain a clock signal for. Defaults to `"sys"`.
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domain : str
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Clock domain to obtain a clock signal for. Defaults to `"sync"`.
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"""
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def __init__(self, cd="sys"):
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def __init__(self, domain="sync"):
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super().__init__()
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if not isinstance(cd, str):
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raise TypeError("Clock domain name must be a string, not {!r}".format(cd))
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self.cd = cd
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if not isinstance(domain, str):
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raise TypeError("Clock domain name must be a string, not {!r}".format(domain))
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self.domain = domain
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def __repr__(self):
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return "(clk {})".format(self.cd)
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return "(clk {})".format(self.domain)
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class ResetSignal(Value):
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@ -610,17 +593,17 @@ class ResetSignal(Value):
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Parameters
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----------
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cd : str
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Clock domain to obtain a reset signal for. Defaults to `"sys"`.
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domain : str
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Clock domain to obtain a reset signal for. Defaults to `"sync"`.
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"""
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def __init__(self, cd="sys"):
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def __init__(self, domain="sync"):
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super().__init__()
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if not isinstance(cd, str):
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raise TypeError("Clock domain name must be a string, not {!r}".format(cd))
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self.cd = cd
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if not isinstance(domain, str):
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raise TypeError("Clock domain name must be a string, not {!r}".format(domain))
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self.domain = domain
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def __repr__(self):
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return "(rst {})".format(self.cd)
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return "(reset {})".format(self.domain)
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class Statement:
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0
nmigen/test/__init__.py
Normal file
0
nmigen/test/__init__.py
Normal file
358
nmigen/test/test_fhdl.py
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358
nmigen/test/test_fhdl.py
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@ -0,0 +1,358 @@
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import unittest
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from nmigen.fhdl.ast import *
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class ValueTestCase(unittest.TestCase):
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def test_wrap(self):
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self.assertIsInstance(Value.wrap(0), Const)
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self.assertIsInstance(Value.wrap(True), Const)
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c = Const(0)
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self.assertIs(Value.wrap(c), c)
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with self.assertRaises(TypeError):
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Value.wrap("str")
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def test_bool(self):
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with self.assertRaises(TypeError):
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if Const(0):
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pass
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def test_len(self):
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self.assertEqual(len(Const(10)), 4)
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def test_getitem_int(self):
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s1 = Const(10)[0]
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self.assertIsInstance(s1, Slice)
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self.assertEqual(s1.start, 0)
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self.assertEqual(s1.end, 1)
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s2 = Const(10)[-1]
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self.assertIsInstance(s2, Slice)
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self.assertEqual(s2.start, 3)
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self.assertEqual(s2.end, 4)
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with self.assertRaises(IndexError):
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Const(10)[5]
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def test_getitem_slice(self):
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s1 = Const(10)[1:3]
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self.assertIsInstance(s1, Slice)
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self.assertEqual(s1.start, 1)
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self.assertEqual(s1.end, 3)
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s2 = Const(10)[1:-2]
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self.assertIsInstance(s2, Slice)
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self.assertEqual(s2.start, 1)
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self.assertEqual(s2.end, 2)
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s3 = Const(31)[::2]
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self.assertIsInstance(s3, Cat)
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self.assertIsInstance(s3.operands[0], Slice)
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self.assertEqual(s3.operands[0].start, 0)
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self.assertEqual(s3.operands[0].end, 1)
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self.assertIsInstance(s3.operands[1], Slice)
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self.assertEqual(s3.operands[1].start, 2)
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self.assertEqual(s3.operands[1].end, 3)
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self.assertIsInstance(s3.operands[2], Slice)
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self.assertEqual(s3.operands[2].start, 4)
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self.assertEqual(s3.operands[2].end, 5)
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def test_getitem_wrong(self):
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with self.assertRaises(TypeError):
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Const(31)["str"]
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class ConstTestCase(unittest.TestCase):
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def test_bits_sign(self):
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self.assertEqual(Const(0).bits_sign(), (0, False))
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self.assertEqual(Const(1).bits_sign(), (1, False))
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self.assertEqual(Const(10).bits_sign(), (4, False))
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self.assertEqual(Const(-10).bits_sign(), (4, True))
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self.assertEqual(Const(1, 4).bits_sign(), (4, False))
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self.assertEqual(Const(1, (4, True)).bits_sign(), (4, True))
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with self.assertRaises(TypeError):
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Const(1, -1)
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def test_value(self):
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self.assertEqual(Const(10).value, 10)
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def test_repr(self):
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self.assertEqual(repr(Const(10)), "(const 4'd10)")
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self.assertEqual(repr(Const(-10)), "(const 4'sd-10)")
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def test_hash(self):
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with self.assertRaises(TypeError):
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hash(Const(0))
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class OperatorTestCase(unittest.TestCase):
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def test_invert(self):
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v = ~Const(0, 4)
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self.assertEqual(repr(v), "(~ (const 4'd0))")
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self.assertEqual(v.bits_sign(), (4, False))
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def test_neg(self):
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v1 = -Const(0, (4, False))
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self.assertEqual(repr(v1), "(- (const 4'd0))")
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self.assertEqual(v1.bits_sign(), (5, True))
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v2 = -Const(0, (4, True))
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self.assertEqual(repr(v2), "(- (const 4'sd0))")
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self.assertEqual(v2.bits_sign(), (4, True))
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def test_add(self):
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v1 = Const(0, (4, False)) + Const(0, (6, False))
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self.assertEqual(repr(v1), "(+ (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (7, False))
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v2 = Const(0, (4, True)) + Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (7, True))
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v3 = Const(0, (4, True)) + Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (6, True))
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v4 = Const(0, (4, False)) + Const(0, (4, True))
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self.assertEqual(v4.bits_sign(), (6, True))
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v5 = 10 + Const(0, 4)
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self.assertEqual(v5.bits_sign(), (5, False))
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def test_sub(self):
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v1 = Const(0, (4, False)) - Const(0, (6, False))
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self.assertEqual(repr(v1), "(- (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (7, False))
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v2 = Const(0, (4, True)) - Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (7, True))
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v3 = Const(0, (4, True)) - Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (6, True))
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v4 = Const(0, (4, False)) - Const(0, (4, True))
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self.assertEqual(v4.bits_sign(), (6, True))
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v5 = 10 - Const(0, 4)
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self.assertEqual(v5.bits_sign(), (5, False))
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def test_mul(self):
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v1 = Const(0, (4, False)) * Const(0, (6, False))
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self.assertEqual(repr(v1), "(* (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (10, False))
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v2 = Const(0, (4, True)) * Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (9, True))
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v3 = Const(0, (4, True)) * Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (8, True))
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v5 = 10 * Const(0, 4)
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self.assertEqual(v5.bits_sign(), (8, False))
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def test_and(self):
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v1 = Const(0, (4, False)) & Const(0, (6, False))
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self.assertEqual(repr(v1), "(& (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (6, False))
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v2 = Const(0, (4, True)) & Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (6, True))
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v3 = Const(0, (4, True)) & Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (5, True))
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v4 = Const(0, (4, False)) & Const(0, (4, True))
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self.assertEqual(v4.bits_sign(), (5, True))
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v5 = 10 & Const(0, 4)
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self.assertEqual(v5.bits_sign(), (4, False))
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def test_or(self):
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v1 = Const(0, (4, False)) | Const(0, (6, False))
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self.assertEqual(repr(v1), "(| (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (6, False))
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v2 = Const(0, (4, True)) | Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (6, True))
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v3 = Const(0, (4, True)) | Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (5, True))
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v4 = Const(0, (4, False)) | Const(0, (4, True))
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self.assertEqual(v4.bits_sign(), (5, True))
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v5 = 10 | Const(0, 4)
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self.assertEqual(v5.bits_sign(), (4, False))
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def test_xor(self):
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v1 = Const(0, (4, False)) ^ Const(0, (6, False))
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self.assertEqual(repr(v1), "(^ (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (6, False))
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v2 = Const(0, (4, True)) ^ Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (6, True))
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v3 = Const(0, (4, True)) ^ Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (5, True))
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v4 = Const(0, (4, False)) ^ Const(0, (4, True))
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self.assertEqual(v4.bits_sign(), (5, True))
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v5 = 10 ^ Const(0, 4)
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self.assertEqual(v5.bits_sign(), (4, False))
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def test_lt(self):
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v = Const(0, 4) < Const(0, 6)
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self.assertEqual(repr(v), "(< (const 4'd0) (const 6'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_le(self):
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v = Const(0, 4) <= Const(0, 6)
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self.assertEqual(repr(v), "(<= (const 4'd0) (const 6'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_gt(self):
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v = Const(0, 4) > Const(0, 6)
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self.assertEqual(repr(v), "(> (const 4'd0) (const 6'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_ge(self):
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v = Const(0, 4) >= Const(0, 6)
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self.assertEqual(repr(v), "(>= (const 4'd0) (const 6'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_eq(self):
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v = Const(0, 4) == Const(0, 6)
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self.assertEqual(repr(v), "(== (const 4'd0) (const 6'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_ne(self):
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v = Const(0, 4) != Const(0, 6)
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self.assertEqual(repr(v), "(!= (const 4'd0) (const 6'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_mux(self):
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s = Const(0)
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v1 = Mux(s, Const(0, (4, False)), Const(0, (6, False)))
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self.assertEqual(repr(v1), "(m (const 0'd0) (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (6, False))
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v2 = Mux(s, Const(0, (4, True)), Const(0, (6, True)))
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self.assertEqual(v2.bits_sign(), (6, True))
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v3 = Mux(s, Const(0, (4, True)), Const(0, (4, False)))
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self.assertEqual(v3.bits_sign(), (5, True))
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v4 = Mux(s, Const(0, (4, False)), Const(0, (4, True)))
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self.assertEqual(v4.bits_sign(), (5, True))
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def test_bool(self):
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v = Const(0).bool()
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self.assertEqual(repr(v), "(b (const 0'd0))")
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self.assertEqual(v.bits_sign(), (1, False))
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def test_hash(self):
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with self.assertRaises(TypeError):
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hash(Const(0) + Const(0))
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class SliceTestCase(unittest.TestCase):
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def test_bits_sign(self):
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s1 = Const(10)[2]
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self.assertEqual(s1.bits_sign(), (1, False))
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s2 = Const(-10)[0:2]
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||||
self.assertEqual(s2.bits_sign(), (2, False))
|
||||
|
||||
def test_repr(self):
|
||||
s1 = Const(10)[2]
|
||||
self.assertEqual(repr(s1), "(slice (const 4'd10) 2:3)")
|
||||
|
||||
|
||||
class CatTestCase(unittest.TestCase):
|
||||
def test_bits_sign(self):
|
||||
c1 = Cat(Const(10))
|
||||
self.assertEqual(c1.bits_sign(), (4, False))
|
||||
c2 = Cat(Const(10), Const(1))
|
||||
self.assertEqual(c2.bits_sign(), (5, False))
|
||||
c3 = Cat(Const(10), Const(1), Const(0))
|
||||
self.assertEqual(c3.bits_sign(), (5, False))
|
||||
|
||||
def test_repr(self):
|
||||
c1 = Cat(Const(10), Const(1))
|
||||
self.assertEqual(repr(c1), "(cat (const 4'd10) (const 1'd1))")
|
||||
|
||||
|
||||
class ReplTestCase(unittest.TestCase):
|
||||
def test_bits_sign(self):
|
||||
r1 = Repl(Const(10), 3)
|
||||
self.assertEqual(r1.bits_sign(), (12, False))
|
||||
|
||||
def test_count_wrong(self):
|
||||
with self.assertRaises(TypeError):
|
||||
Repl(Const(10), -1)
|
||||
with self.assertRaises(TypeError):
|
||||
Repl(Const(10), "str")
|
||||
|
||||
def test_repr(self):
|
||||
r1 = Repl(Const(10), 3)
|
||||
self.assertEqual(repr(r1), "(repl (const 4'd10) 3)")
|
||||
|
||||
|
||||
class SignalTestCase(unittest.TestCase):
|
||||
def test_bits_sign(self):
|
||||
s1 = Signal()
|
||||
self.assertEqual(s1.bits_sign(), (1, False))
|
||||
s2 = Signal(2)
|
||||
self.assertEqual(s2.bits_sign(), (2, False))
|
||||
s3 = Signal((2, False))
|
||||
self.assertEqual(s3.bits_sign(), (2, False))
|
||||
s4 = Signal((2, True))
|
||||
self.assertEqual(s4.bits_sign(), (2, True))
|
||||
s5 = Signal(max=16)
|
||||
self.assertEqual(s5.bits_sign(), (4, False))
|
||||
s6 = Signal(min=4, max=16)
|
||||
self.assertEqual(s6.bits_sign(), (4, False))
|
||||
s7 = Signal(min=-4, max=16)
|
||||
self.assertEqual(s7.bits_sign(), (5, True))
|
||||
s8 = Signal(min=-20, max=16)
|
||||
self.assertEqual(s8.bits_sign(), (6, True))
|
||||
|
||||
with self.assertRaises(ValueError):
|
||||
Signal(min=10, max=4)
|
||||
with self.assertRaises(ValueError):
|
||||
Signal(2, min=10)
|
||||
with self.assertRaises(TypeError):
|
||||
Signal(-10)
|
||||
|
||||
def test_name(self):
|
||||
s1 = Signal()
|
||||
self.assertEqual(s1.name, "s1")
|
||||
s2 = Signal(name="sig")
|
||||
self.assertEqual(s2.name, "sig")
|
||||
|
||||
def test_reset(self):
|
||||
s1 = Signal(4, reset=0b111, reset_less=True)
|
||||
self.assertEqual(s1.reset, 0b111)
|
||||
self.assertEqual(s1.reset_less, True)
|
||||
|
||||
def test_attrs(self):
|
||||
s1 = Signal()
|
||||
self.assertEqual(s1.attrs, {})
|
||||
s2 = Signal(attrs={"no_retiming": True})
|
||||
self.assertEqual(s2.attrs, {"no_retiming": True})
|
||||
|
||||
def test_repr(self):
|
||||
s1 = Signal()
|
||||
self.assertEqual(repr(s1), "(sig s1)")
|
||||
|
||||
def test_like(self):
|
||||
s1 = Signal.like(Signal(4))
|
||||
self.assertEqual(s1.bits_sign(), (4, False))
|
||||
s2 = Signal.like(Signal(min=-15))
|
||||
self.assertEqual(s2.bits_sign(), (5, True))
|
||||
s3 = Signal.like(Signal(4, reset=0b111, reset_less=True))
|
||||
self.assertEqual(s3.reset, 0b111)
|
||||
self.assertEqual(s3.reset_less, True)
|
||||
s4 = Signal.like(Signal(attrs={"no_retiming": True}))
|
||||
self.assertEqual(s4.attrs, {"no_retiming": True})
|
||||
s5 = Signal.like(10)
|
||||
self.assertEqual(s5.bits_sign(), (4, False))
|
||||
|
||||
|
||||
class ClockSignalTestCase(unittest.TestCase):
|
||||
def test_domain(self):
|
||||
s1 = ClockSignal()
|
||||
self.assertEqual(s1.domain, "sync")
|
||||
s2 = ClockSignal("pix")
|
||||
self.assertEqual(s2.domain, "pix")
|
||||
|
||||
with self.assertRaises(TypeError):
|
||||
ClockSignal(1)
|
||||
|
||||
def test_repr(self):
|
||||
s1 = ClockSignal()
|
||||
self.assertEqual(repr(s1), "(clk sync)")
|
||||
|
||||
|
||||
class ResetSignalTestCase(unittest.TestCase):
|
||||
def test_domain(self):
|
||||
s1 = ResetSignal()
|
||||
self.assertEqual(s1.domain, "sync")
|
||||
s2 = ResetSignal("pix")
|
||||
self.assertEqual(s2.domain, "pix")
|
||||
|
||||
with self.assertRaises(TypeError):
|
||||
ResetSignal(1)
|
||||
|
||||
def test_repr(self):
|
||||
s1 = ResetSignal()
|
||||
self.assertEqual(repr(s1), "(reset sync)")
|
||||
Loading…
Reference in a new issue