vendor._lattice: add Nexus support.
Co-authored-by: Nate Slager <slagernate@gmail.com>
This commit is contained in:
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@ -31,10 +31,9 @@ See the [Language guide](https://amaranth-lang.org/docs/amaranth/latest/guide.ht
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Amaranth can be used to target any FPGA or ASIC process that accepts behavioral Verilog-2001 as input. It also offers extended support for many FPGA families, providing toolchain integration, abstractions for device-specific primitives, and more. Specifically:
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* Lattice iCE40 (toolchains: **Yosys+nextpnr**, LSE-iCECube2, Synplify-iCECube2);
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* Lattice MachXO2 (toolchains: Diamond);
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* Lattice MachXO3L (toolchains: Diamond);
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* Lattice MachXO2, MachXO3L (toolchains: **Yosys+nextpnr**, Diamond);
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* Lattice ECP5 (toolchains: **Yosys+nextpnr**, Diamond);
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* Lattice Nexus (toolchains: **Yosys+nextpnr**, Diamond);
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* Lattice Nexus (toolchains: **Yosys+nextpnr**, Radiant);
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* AMD Virtex, Virtex E, Spartan 2, Spartan 2E (toolchains: ISE);
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* AMD Virtex II, Virtex II Pro (toolchains: ISE);
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* AMD Spartan 3, Spartan 3E, Spartan 3A, Spartan 3AN, Spartan 3A DSP (toolchains: ISE);
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@ -205,6 +205,47 @@ class DDRBufferMachXO2(io.DDRBuffer):
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return m
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class DDRBufferNexus(io.DDRBuffer):
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def elaborate(self, platform):
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m = Module()
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m.submodules.buf = buf = InnerBuffer(self.direction, self.port)
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inv_mask = sum(inv << bit for bit, inv in enumerate(self.port.invert))
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if self.direction is not io.Direction.Output:
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i0_inv = Signal(len(self.port))
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i1_inv = Signal(len(self.port))
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for bit in range(len(self.port)):
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m.submodules[f"i_ddr{bit}"] = Instance("IDDRX1",
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i_SCLK=ClockSignal(self.i_domain),
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i_RST=Const(0),
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i_D=buf.i[bit],
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o_Q0=i0_inv[bit],
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o_Q1=i1_inv[bit],
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)
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m.d.comb += self.i[0].eq(i0_inv ^ inv_mask)
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m.d.comb += self.i[1].eq(i1_inv ^ inv_mask)
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if self.direction is not io.Direction.Input:
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o0_inv = Signal(len(self.port))
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o1_inv = Signal(len(self.port))
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m.d.comb += [
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o0_inv.eq(self.o[0] ^ inv_mask),
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o1_inv.eq(self.o[1] ^ inv_mask),
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]
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for bit in range(len(self.port)):
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m.submodules[f"o_ddr{bit}"] = Instance("ODDRX1",
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i_SCLK=ClockSignal(self.o_domain),
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i_RST=Const(0),
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i_D0=o0_inv[bit],
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i_D1=o1_inv[bit],
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o_Q=buf.o[bit],
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)
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_make_oereg(m, self.o_domain, ~self.oe, buf.t)
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return m
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class LatticePlatform(TemplatedPlatform):
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"""
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.. rubric:: Trellis toolchain (ECP5, MachXO2, MachXO3)
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@ -236,6 +277,35 @@ class LatticePlatform(TemplatedPlatform):
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* ``{{name}}.bit``: binary bitstream.
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* ``{{name}}.svf``: JTAG programming vector.
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.. rubric:: Oxide toolchain (Nexus)
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Required tools:
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* ``yosys``
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* ``nextpnr-nexus``
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* ``prjoxide``
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The environment is populated by running the script specified in the environment variable
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``AMARANTH_ENV_OXIDE``, if present.
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Available overrides:
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* ``verbose``: enables logging of informational messages to standard error.
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* ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
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* ``synth_opts``: adds options for ``synth_nexus`` Yosys command.
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* ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
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* ``script_after_synth``: inserts commands after ``synth_nexus`` in Yosys script.
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* ``yosys_opts``: adds extra options for ``yosys``.
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* ``nextpnr_opts``: adds extra options for ``nextpnr-nexus``.
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* ``prjoxide_opts``: adds extra options for ``prjoxide``.
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* ``add_preferences``: inserts commands at the end of the PDC file.
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Build products:
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* ``{{name}}.rpt``: Yosys log.
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* ``{{name}}.json``: synthesized RTL.
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* ``{{name}}.tim``: nextpnr log.
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* ``{{name}}.config``: ASCII bitstream.
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* ``{{name}}.bit``: binary bitstream.
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* ``{{name}}.xcf``: JTAG programming vector.
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.. rubric:: Diamond toolchain (ECP5, MachXO2, MachXO3)
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Required tools:
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@ -263,6 +333,30 @@ class LatticePlatform(TemplatedPlatform):
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* ``{{name}}.svf``: JTAG programming vector (ECP5 only).
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* ``{{name}}_flash.svf``: JTAG programming vector for FLASH programming (MachXO2, MachXO3 only).
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* ``{{name}}_sram.svf``: JTAG programming vector for SRAM programming (MachXO2, MachXO3 only).
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.. rubric:: Radiant toolchain (Nexus)
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Required tools:
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* ``radiantc``
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The environment is populated by running the script specified in the environment variable
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``AMARANTH_ENV_RADIANT``, if present. On Linux, radiant_env as provided by Radiant
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itself is a good candidate. On Windows, the following script (named ``radiant_env.bat``,
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for instance) is known to work::
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@echo off
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set PATH=C:\\lscc\\radiant\\%RADIANT_VERSION%\\bin\\nt64;%PATH%
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Available overrides:
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* ``script_project``: inserts commands before ``prj_save`` in Tcl script.
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* ``script_after_export``: inserts commands after ``prj_run Export`` in Tcl script.
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* ``add_constraints``: inserts commands at the end of the SDC file.
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* ``add_preferences``: inserts commands at the end of the PDC file.
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Build products:
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* ``{{name}}_impl/{{name}}_impl.htm``: consolidated log.
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* ``{{name}}.bit``: binary bitstream.
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* ``{{name}}.xcf``: JTAG programming vector. (if using ``programmer``)
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"""
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toolchain = None # selected when creating platform
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@ -390,6 +484,77 @@ class LatticePlatform(TemplatedPlatform):
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"""
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]
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# Oxide templates
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_oxide_required_tools = [
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"yosys",
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"nextpnr-nexus",
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"prjoxide"
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]
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_oxide_file_templates = {
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**TemplatedPlatform.build_script_templates,
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"{{name}}.il": r"""
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# {{autogenerated}}
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{{emit_rtlil()}}
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""",
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"{{name}}.debug.v": r"""
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/* {{autogenerated}} */
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{{emit_debug_verilog()}}
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""",
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"{{name}}.ys": r"""
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# {{autogenerated}}
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{% for file in platform.iter_files(".v") -%}
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read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
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{% endfor %}
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{% for file in platform.iter_files(".sv") -%}
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read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
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{% endfor %}
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{% for file in platform.iter_files(".il") -%}
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read_ilang {{file}}
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{% endfor %}
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read_ilang {{name}}.il
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delete w:$verilog_initial_trigger
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{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
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synth_nexus {{get_override("synth_opts")|options}} -top {{name}}
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{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
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write_json {{name}}.json
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""",
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"{{name}}.pdc": r"""
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# {{autogenerated}}
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{% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
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ldc_set_location -site {{ '{' }}{{pin_name}}{{ '}' }} {{'['}}get_ports {{port_name}}{{']'}}
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{% if attrs -%}
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ldc_set_port -iobuf {{ '{' }}{%- for key, value in attrs.items() %}{{key}}={{value}} {% endfor %}{{ '}' }} {{'['}}get_ports {{port_name}}{{']'}}
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{% endif %}
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{% endfor %}
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{{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
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"""
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}
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_oxide_command_templates = [
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r"""
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{{invoke_tool("yosys")}}
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{{get_override("yosys_opts")|options}}
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-l {{name}}.rpt
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{{name}}.ys
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""",
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r"""
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{{invoke_tool("nextpnr-nexus")}}
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{{get_override("nextpnr_opts")|options}}
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--log {{name}}.tim
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--device {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}}
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--pdc {{name}}.pdc
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--json {{name}}.json
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--fasm {{name}}.fasm
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""",
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r"""
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{{invoke_tool("prjoxide")}}
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{{verbose("--verbose")}}
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{{get_override("prjoxide_opts")|options}}
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pack {{name}}.fasm
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{{name}}.bit
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"""
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]
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# Diamond templates
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_diamond_required_tools = [
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@ -511,6 +676,76 @@ class LatticePlatform(TemplatedPlatform):
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""",
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]
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# Radiant templates
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_radiant_required_tools = [
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"radiantc",
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]
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_radiant_file_templates = {
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**TemplatedPlatform.build_script_templates,
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"build_{{name}}.sh": r"""
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# {{autogenerated}}
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set -e{{verbose("x")}}
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if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
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{{emit_commands("sh")}}
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""",
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"{{name}}.v": r"""
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/* {{autogenerated}} */
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{{emit_verilog()}}
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""",
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"{{name}}.debug.v": r"""
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/* {{autogenerated}} */
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{{emit_debug_verilog()}}
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""",
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"{{name}}.tcl": r"""
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prj_create -name {{name}} -impl impl \
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-dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
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-synthesis synplify
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{% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
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prj_add_source {{file|tcl_quote}}
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{% endfor %}
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prj_add_source {{name}}.v
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prj_add_source {{name}}.sdc
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prj_add_source {{name}}.pdc
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prj_set_impl_opt top \"{{name}}\"
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{{get_override("script_project")|default("# (script_project placeholder)")}}
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prj_save
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prj_run Synthesis -impl impl -forceOne
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prj_run Map -impl impl
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prj_run PAR -impl impl
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prj_run Export -impl impl -task Bitgen
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{{get_override("script_after_export")|default("# (script_after_export placeholder)")}}
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""",
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# Pre-synthesis SDC constraints
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"{{name}}.sdc": r"""
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{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
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{% if port_signal is not none -%}
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create_clock -name {{port_signal.name|tcl_quote}} -period {{1000000000/frequency}} [get_ports {{port_signal.name}}]
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{% else -%}
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create_clock -name {{net_signal.name|tcl_quote}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")}}]
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{% endif %}
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{% endfor %}
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{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
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""",
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# Physical PDC contraints
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"{{name}}.pdc": r"""
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{% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
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ldc_set_location -site "{{pin_name}}" [get_ports {{port_name|tcl_quote}}]
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{% if attrs -%}
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ldc_set_port -iobuf { {%- for key, value in attrs.items() %} {{key}}={{value}}{% endfor %} } [get_ports {{port_name|tcl_quote}}]
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{% endif %}
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{% endfor %}
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{{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
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""",
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}
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_radiant_command_templates = [
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# These don't have any usable command-line option overrides.
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r"""
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{{invoke_tool("radiantc")}}
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{{name}}.tcl
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""",
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]
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# Common logic
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def __init__(self, *, toolchain=None):
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@ -521,16 +756,23 @@ class LatticePlatform(TemplatedPlatform):
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self.family = "ecp5"
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elif device.startswith(("lcmxo2-", "lcmxo3l", "lcmxo3d", "lamxo2-", "lamxo3l", "lamxo3d", "lfmnx-")):
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self.family = "machxo2"
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elif device.startswith(("lifcl-", "lfcpnx-", "lfd2nx-", "lfmxo5-", "ut24c")):
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self.family = "nexus"
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else:
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raise ValueError(f"Device '{self.device}' is not recognized")
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if toolchain is None:
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if self.family == "ecp5":
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if self.family == "nexus":
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toolchain = "Oxide"
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elif self.family == "ecp5":
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toolchain = "Trellis"
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else:
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toolchain = "Diamond"
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assert toolchain in ("Trellis", "Diamond")
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if self.family == "nexus":
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assert toolchain in ("Oxide", "Radiant")
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else:
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assert toolchain in ("Trellis", "Diamond")
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self.toolchain = toolchain
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@property
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@ -540,27 +782,39 @@ class LatticePlatform(TemplatedPlatform):
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return self._trellis_required_tools_ecp5
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elif self.family == "machxo2":
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return self._trellis_required_tools_machxo2
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if self.toolchain == "Oxide":
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return self._oxide_required_tools
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if self.toolchain == "Diamond":
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return self._diamond_required_tools
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if self.toolchain == "Radiant":
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return self._radiant_required_tools
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assert False
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@property
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def file_templates(self):
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if self.toolchain == "Trellis":
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return self._trellis_file_templates
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if self.toolchain == "Oxide":
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return self._oxide_file_templates
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if self.toolchain == "Diamond":
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return self._diamond_file_templates
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if self.toolchain == "Radiant":
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return self._radiant_file_templates
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assert False
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@property
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def command_templates(self):
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if self.toolchain == "Trellis":
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return self._trellis_command_templates
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if self.toolchain == "Oxide":
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return self._oxide_command_templates
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if self.toolchain == "Diamond":
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if self.family == "ecp5":
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return self._diamond_command_templates_ecp5
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if self.family == "machxo2":
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return self._diamond_command_templates_machxo2
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if self.toolchain == "Radiant":
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return self._radiant_command_templates
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assert False
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# These numbers were extracted from
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@ -585,6 +839,9 @@ class LatticePlatform(TemplatedPlatform):
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# It can have a range of frequencies.
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assert self.osch_frequency in self._supported_osch_freqs
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return Clock(int(self.osch_frequency * 1e6))
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if self.default_clk == "OSCA":
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# Internal high-speed oscillator on Nexus devices.
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return Clock(450e6 / self.osca_div)
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# Otherwise, use the defined Clock resource.
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return super().default_clk_constraint
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@ -615,7 +872,22 @@ class LatticePlatform(TemplatedPlatform):
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.format(osch_freq, self._supported_osch_freqs))
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osch_freq_param = f"{float(osch_freq):.2f}"
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clk_i = Signal()
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m.submodules += [ Instance("OSCH", p_NOM_FREQ=osch_freq_param, i_STDBY=Const(0), o_OSC=clk_i, o_SEDSTDBY=Signal()) ]
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m.submodules += Instance("OSCH", p_NOM_FREQ=osch_freq_param, i_STDBY=Const(0), o_OSC=clk_i, o_SEDSTDBY=Signal())
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elif self.default_clk == "OSCA":
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if not hasattr(self, "osca_div"):
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raise ValueError("OSCA divider (osca_div) must be an integer between 2 "
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"and 256")
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if not isinstance(self.osca_div, int) or self.osca_div < 2 or self.osca_div > 256:
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raise ValueError("OSCA divider (osca_div) must be an integer between 2 "
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"and 256, not {!r}"
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.format(self.osca_div))
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clk_i = Signal()
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m.submodules += Instance("OSCA",
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p_HF_CLK_DIV=str(self.osca_div - 1),
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i_HFOUTEN=Const(1),
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i_HFSDSCEN=Const(0), # HFSDSCEN used for SED/SEC detector
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o_HFCLKOUT=clk_i,
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)
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else:
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clk_i = self.request(self.default_clk).i
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if self.default_rst is not None:
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@ -627,14 +899,40 @@ class LatticePlatform(TemplatedPlatform):
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gsr1 = Signal()
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# There is no end-of-startup signal on Lattice, but PUR is released after IOB enable, so
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# a simple reset synchronizer (with PUR as the asynchronous reset) does the job.
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m.submodules += [
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Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=~rst_i, o_Q=gsr0),
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Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=gsr0, o_Q=gsr1),
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# Although we already synchronize the reset input to user clock, SGSR has dedicated
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# clock routing to the center of the FPGA; use that just in case it turns out to be
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# more reliable. (None of this is documented.)
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Instance("SGSR", i_CLK=clk_i, i_GSR=gsr1),
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]
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if self.family == "nexus":
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# On Nexus all the D-type FFs have either an synchronous or asynchronous preset.
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||||
# Here we build a simple reset synchronizer from D-type FFs with a positive-level
|
||||
# asynchronous preset which we tie low
|
||||
m.submodules += [
|
||||
Instance(
|
||||
"FD1P3BX",
|
||||
p_GSR="DISABLED",
|
||||
i_CK=clk_i,
|
||||
i_D=~rst_i,
|
||||
i_SP=Const(1),
|
||||
i_PD=Const(0),
|
||||
o_Q=gsr0,
|
||||
),
|
||||
Instance(
|
||||
"FD1P3BX",
|
||||
p_GSR="DISABLED",
|
||||
i_CK=clk_i,
|
||||
i_D=gsr0,
|
||||
i_SP=Const(1),
|
||||
i_PD=Const(0),
|
||||
o_Q=gsr1,
|
||||
),
|
||||
Instance("GSR", p_SYNCMODE="SYNC", i_CLK=clk_i, i_GSR_N=gsr1),
|
||||
]
|
||||
else:
|
||||
m.submodules += [
|
||||
Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=~rst_i, o_Q=gsr0),
|
||||
Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=gsr0, o_Q=gsr1),
|
||||
# Although we already synchronize the reset input to user clock, SGSR has dedicated
|
||||
# clock routing to the center of the FPGA; use that just in case it turns out to be
|
||||
# more reliable. (None of this is documented.)
|
||||
Instance("SGSR", i_CLK=clk_i, i_GSR=gsr1),
|
||||
]
|
||||
# GSR implicitly connects to every appropriate storage element. As such, the sync
|
||||
# domain is reset-less; domains driven by other clocks would need to have dedicated
|
||||
# reset circuitry or otherwise meet setup/hold constraints on their own.
|
||||
|
|
@ -652,6 +950,8 @@ class LatticePlatform(TemplatedPlatform):
|
|||
result = DDRBufferECP5(buffer.direction, buffer.port)
|
||||
elif self.family == "machxo2":
|
||||
result = DDRBufferMachXO2(buffer.direction, buffer.port)
|
||||
elif self.family == "nexus":
|
||||
result = DDRBufferNexus(buffer.direction, buffer.port)
|
||||
else:
|
||||
raise NotImplementedError # :nocov:
|
||||
else:
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ Lattice
|
|||
|
||||
.. currentmodule:: amaranth.vendor
|
||||
|
||||
The :class:`LatticePlatform` class provides a base platform to support Lattice toolchains (not including iCE40 devices, which are supported by :class:`SiliconBluePlatform`). Currently supported devices include ECP5, MachXO2, and MachXO3L.
|
||||
The :class:`LatticePlatform` class provides a base platform to support Lattice toolchains (not including iCE40 devices, which are supported by :class:`SiliconBluePlatform`). Currently supported devices include ECP5, MachXO2, MachXO3L, and Nexus.
|
||||
|
||||
The Trellis and Diamond toolchains are supported.
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue