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hdl.{ast,dsl}: allow whitespace in bit patterns.

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Fixes #316.
This commit is contained in:
whitequark 2020-02-04 07:54:54 +00:00
parent a295e3599c
commit dfcf7938ea
4 changed files with 21 additions and 9 deletions
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10
nmigen/hdl/ast.py
View file

@ -357,11 +357,12 @@ class Value(metaclass=ABCMeta):
raise SyntaxError("Match pattern must be an integer, a string, or an enumeration, "
"not {!r}"
.format(pattern))
if isinstance(pattern, str) and any(bit not in "01-" for bit in pattern):
if isinstance(pattern, str) and any(bit not in "01- \t" for bit in pattern):
raise SyntaxError("Match pattern '{}' must consist of 0, 1, and - (don't care) "
"bits"
"bits, and may include whitespace"
.format(pattern))
if isinstance(pattern, str) and len(pattern) != len(self):
if (isinstance(pattern, str) and
len("".join(pattern.split())) != len(self)):
raise SyntaxError("Match pattern '{}' must have the same width as match value "
"(which is {})"
.format(pattern, len(self)))
@ -372,6 +373,7 @@ class Value(metaclass=ABCMeta):
SyntaxWarning, stacklevel=3)
continue
if isinstance(pattern, str):
pattern = "".join(pattern.split()) # remove whitespace
mask = int(pattern.replace("0", "1").replace("-", "0"), 2)
pattern = int(pattern.replace("-", "0"), 2)
matches.append((self & mask) == pattern)
@ -1300,7 +1302,7 @@ class Switch(Statement):
new_keys = ()
for key in keys:
if isinstance(key, str):
pass
key = "".join(key.split()) # remove whitespace
elif isinstance(key, int):
key = format(key, "b").rjust(len(self.test), "0")
elif isinstance(key, Enum):

8
nmigen/hdl/dsl.py
View file

@ -301,10 +301,12 @@ class Module(_ModuleBuilderRoot, Elaboratable):
raise SyntaxError("Case pattern must be an integer, a string, or an enumeration, "
"not {!r}"
.format(pattern))
if isinstance(pattern, str) and any(bit not in "01-" for bit in pattern):
raise SyntaxError("Case pattern '{}' must consist of 0, 1, and - (don't care) bits"
if isinstance(pattern, str) and any(bit not in "01- \t" for bit in pattern):
raise SyntaxError("Case pattern '{}' must consist of 0, 1, and - (don't care) "
"bits, and may include whitespace"
.format(pattern))
if isinstance(pattern, str) and len(pattern) != len(switch_data["test"]):
if (isinstance(pattern, str) and
len("".join(pattern.split())) != len(switch_data["test"])):
raise SyntaxError("Case pattern '{}' must have the same width as switch value "
"(which is {})"
.format(pattern, len(switch_data["test"])))

6
nmigen/test/test_hdl_ast.py
View file

@ -464,6 +464,9 @@ class OperatorTestCase(FHDLTestCase):
self.assertRepr(s.matches("10--"), """
(== (& (sig s) (const 4'd12)) (const 4'd8))
""")
self.assertRepr(s.matches("1 0--"), """
(== (& (sig s) (const 4'd12)) (const 4'd8))
""")
def test_matches_enum(self):
s = Signal(SignedEnum)
@ -484,7 +487,8 @@ class OperatorTestCase(FHDLTestCase):
def test_matches_bits_wrong(self):
s = Signal(4)
with self.assertRaises(SyntaxError,
msg="Match pattern 'abc' must consist of 0, 1, and - (don't care) bits"):
msg="Match pattern 'abc' must consist of 0, 1, and - (don't care) bits, "
"and may include whitespace"):
s.matches("abc")
def test_matches_pattern_wrong(self):

6
nmigen/test/test_hdl_dsl.py
View file

@ -331,12 +331,15 @@ class DSLTestCase(FHDLTestCase):
m.d.comb += self.c1.eq(1)
with m.Case("11--"):
m.d.comb += self.c2.eq(1)
with m.Case("1 0--"):
m.d.comb += self.c2.eq(1)
m._flush()
self.assertRepr(m._statements, """
(
(switch (sig w1)
(case 0011 (eq (sig c1) (const 1'd1)))
(case 11-- (eq (sig c2) (const 1'd1)))
(case 10-- (eq (sig c2) (const 1'd1)))
)
)
""")
@ -435,7 +438,8 @@ class DSLTestCase(FHDLTestCase):
m = Module()
with m.Switch(self.w1):
with self.assertRaises(SyntaxError,
msg="Case pattern 'abc' must consist of 0, 1, and - (don't care) bits"):
msg="Case pattern 'abc' must consist of 0, 1, and - (don't care) bits, "
"and may include whitespace"):
with m.Case("abc"):
pass