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hdl.{ast,dsl}: allow whitespace in bit patterns.

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Fixes #316.
This commit is contained in:
whitequark 2020-02-04 07:54:54 +00:00
parent a295e3599c
commit dfcf7938ea
4 changed files with 21 additions and 9 deletions
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6
nmigen/test/test_hdl_ast.py
View file

@ -464,6 +464,9 @@ class OperatorTestCase(FHDLTestCase):
self.assertRepr(s.matches("10--"), """
(== (& (sig s) (const 4'd12)) (const 4'd8))
""")
self.assertRepr(s.matches("1 0--"), """
(== (& (sig s) (const 4'd12)) (const 4'd8))
""")
def test_matches_enum(self):
s = Signal(SignedEnum)
@ -484,7 +487,8 @@ class OperatorTestCase(FHDLTestCase):
def test_matches_bits_wrong(self):
s = Signal(4)
with self.assertRaises(SyntaxError,
msg="Match pattern 'abc' must consist of 0, 1, and - (don't care) bits"):
msg="Match pattern 'abc' must consist of 0, 1, and - (don't care) bits, "
"and may include whitespace"):
s.matches("abc")
def test_matches_pattern_wrong(self):

6
nmigen/test/test_hdl_dsl.py
View file

@ -331,12 +331,15 @@ class DSLTestCase(FHDLTestCase):
m.d.comb += self.c1.eq(1)
with m.Case("11--"):
m.d.comb += self.c2.eq(1)
with m.Case("1 0--"):
m.d.comb += self.c2.eq(1)
m._flush()
self.assertRepr(m._statements, """
(
(switch (sig w1)
(case 0011 (eq (sig c1) (const 1'd1)))
(case 11-- (eq (sig c2) (const 1'd1)))
(case 10-- (eq (sig c2) (const 1'd1)))
)
)
""")
@ -435,7 +438,8 @@ class DSLTestCase(FHDLTestCase):
m = Module()
with m.Switch(self.w1):
with self.assertRaises(SyntaxError,
msg="Case pattern 'abc' must consist of 0, 1, and - (don't care) bits"):
msg="Case pattern 'abc' must consist of 0, 1, and - (don't care) bits, "
"and may include whitespace"):
with m.Case("abc"):
pass