usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Remove everything deprecated in nmigen 0.1.

Browse source 
Closes #275.
This commit is contained in:
whitequark 2020-01-12 13:59:26 +00:00
parent e4e26717be
commit e18385b613
13 changed files with 208 additions and 240 deletions
Download patch file Download diff file Expand all files Collapse all files

5
nmigen/vendor/lattice_ice40.py vendored
View file

@ -350,16 +350,18 @@ class LatticeICE40Platform(TemplatedPlatform):
rst_i = Const(0)
m = Module()
# Power-on-reset domain
m.domains += ClockDomain("por", reset_less=True, local=True)
delay = int(15e-6 * self.default_clk_frequency)
timer = Signal(max=delay)
timer = Signal(range(delay))
ready = Signal()
m.d.comb += ClockSignal("por").eq(clk_i)
with m.If(timer == delay):
m.d.por += ready.eq(1)
with m.Else():
m.d.por += timer.eq(timer + 1)
# Primary domain
m.domains += ClockDomain("sync")
m.d.comb += ClockSignal("sync").eq(clk_i)
@ -367,6 +369,7 @@ class LatticeICE40Platform(TemplatedPlatform):
m.submodules.reset_sync = ResetSynchronizer(~ready | rst_i, domain="sync")
else:
m.d.comb += ResetSignal("sync").eq(~ready)
return m
def should_skip_port_component(self, port, attrs, component):