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back.pysim: make initial phase configurable.

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This commit is contained in:
whitequark 2018-12-14 16:46:16 +00:00
parent 0ef5ced492
commit e230383aac
2 changed files with 6 additions and 4 deletions
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6
nmigen/back/pysim.py
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@ -250,15 +250,17 @@ class Simulator:
pass pass
self.add_process(sync_process()) self.add_process(sync_process())
def add_clock(self, period, domain="sync"): def add_clock(self, period, phase=None, domain="sync"):
if self._fastest_clock == self._epsilon or period < self._fastest_clock: if self._fastest_clock == self._epsilon or period < self._fastest_clock:
self._fastest_clock = period self._fastest_clock = period
half_period = period / 2 half_period = period / 2
if phase is None:
phase = half_period
clk = self._domains[domain].clk clk = self._domains[domain].clk
def clk_process(): def clk_process():
yield Passive() yield Passive()
yield Delay(half_period) yield Delay(phase)
while True: while True:
yield clk.eq(1) yield clk.eq(1)
yield Delay(half_period) yield Delay(half_period)

4
nmigen/compat/sim/__init__.py
View file

@ -18,7 +18,7 @@ def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name
with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim: with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim:
for domain, period in clocks.items(): for domain, period in clocks.items():
sim.add_clock(period / 1e9, domain) sim.add_clock(period / 1e9, domain=domain)
for domain, process in generators.items(): for domain, process in generators.items():
sim.add_sync_process(process, domain) sim.add_sync_process(process, domain=domain)
sim.run() sim.run()