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hdl._dsl: fix using 0-width Switch with integer keys.

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Fixes #1133.
This commit is contained in:
Wanda 2024-02-14 00:04:56 +01:00 committed by Catherine
parent 5ffb48b5fb
commit e3324e1456
2 changed files with 17 additions and 0 deletions
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2
amaranth/hdl/_dsl.py
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@ -328,6 +328,8 @@ class Module(_ModuleBuilderRoot, Elaboratable):
"expression, not {!r}" "expression, not {!r}"
.format(pattern)) from e .format(pattern)) from e
pattern_len = bits_for(pattern.value) pattern_len = bits_for(pattern.value)
if pattern.value == 0:
pattern_len = 0
if pattern_len > len(switch_data["test"]): if pattern_len > len(switch_data["test"]):
warnings.warn("Case pattern '{!r}' ({}'{:b}) is wider than switch value " warnings.warn("Case pattern '{!r}' ({}'{:b}) is wider than switch value "
"(which has width {}); comparison will never be true" "(which has width {}); comparison will never be true"

15
tests/test_hdl_dsl.py
View file

@ -502,6 +502,21 @@ class DSLTestCase(FHDLTestCase):
m.d.comb += dummy.eq(0) m.d.comb += dummy.eq(0)
self.assertEqual(m._statements, {}) self.assertEqual(m._statements, {})
def test_Switch_zero_width(self):
m = Module()
s = Signal(0)
with m.Switch(s):
with m.Case(0):
m.d.comb += self.c1.eq(1)
m._flush()
self.assertRepr(m._statements["comb"], """
(
(switch (sig s)
(case (eq (sig c1) (const 1'd1)))
)
)
""")
def test_Case_bits_wrong(self): def test_Case_bits_wrong(self):
m = Module() m = Module()
with m.Switch(self.w1): with m.Switch(self.w1):