lib.fifo: add AsyncFIFO and AsyncFIFOBuffered.
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whitequark
parent
12e04e4ee5
commit
e33580cf4c
2 changed files with 258 additions and 53 deletions
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@ -3,44 +3,57 @@ from ..hdl.ast import *
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from ..hdl.dsl import *
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from ..hdl.mem import *
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from ..hdl.ir import *
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from ..hdl.xfrm import *
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from ..hdl.cd import *
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from ..back.pysim import *
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from ..lib.fifo import *
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class FIFOSmokeTestCase(FHDLTestCase):
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def assertSyncFIFOWorks(self, fifo):
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with Simulator(fifo) as sim:
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def assertSyncFIFOWorks(self, fifo, xfrm=lambda x: x):
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with Simulator(xfrm(fifo.get_fragment(None)), vcd_file=open("test.vcd", "w")) as sim:
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sim.add_clock(1e-6)
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def process():
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yield from fifo.write(1)
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yield from fifo.write(2)
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while not (yield fifo.readable):
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yield
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if not fifo.fwft:
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yield fifo.re.eq(1)
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yield
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self.assertEqual((yield from fifo.read()), 1)
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self.assertEqual((yield from fifo.read()), 2)
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sim.add_sync_process(process)
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sim.run()
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def assertAsyncFIFOWorks(self, fifo):
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self.assertSyncFIFOWorks(fifo, xfrm=DomainRenamer({"read": "sync", "write": "sync"}))
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def test_sync_fwft(self):
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fifo = SyncFIFO(width=8, depth=4, fwft=True)
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self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4))
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self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4, fwft=True))
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def test_sync_not_fwft(self):
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fifo = SyncFIFO(width=8, depth=4, fwft=False)
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self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4))
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self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4, fwft=False))
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def test_sync_buffered(self):
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fifo = SyncFIFO(width=8, depth=4, fwft=True)
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self.assertSyncFIFOWorks(SyncFIFOBuffered(width=8, depth=4))
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self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4, fwft=True))
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def test_async(self):
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self.assertAsyncFIFOWorks(AsyncFIFO(width=8, depth=4))
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def test_async_buffered(self):
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self.assertAsyncFIFOWorks(AsyncFIFOBuffered(width=8, depth=3))
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class FIFOModel(FIFOInterface):
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"""
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Non-synthesizable first-in first-out queue, implemented naively as a chain of registers.
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"""
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def __init__(self, width, depth, fwft):
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super().__init__(width, depth)
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def __init__(self, width, depth, fwft, rdomain, wdomain):
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super().__init__(width, depth, fwft)
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self.fwft = fwft
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self.rdomain = rdomain
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self.wdomain = wdomain
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self.replace = Signal()
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self.level = Signal(max=self.depth + 1)
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@ -49,8 +62,8 @@ class FIFOModel(FIFOInterface):
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m = Module()
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storage = Memory(self.width, self.depth)
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wrport = m.submodules.wrport = storage.write_port()
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rdport = m.submodules.rdport = storage.read_port(synchronous=False)
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wrport = m.submodules.wrport = storage.write_port(domain=self.wdomain)
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rdport = m.submodules.rdport = storage.read_port (synchronous=False)
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produce = Signal(max=self.depth)
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consume = Signal(max=self.depth)
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@ -61,8 +74,8 @@ class FIFOModel(FIFOInterface):
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m.d.comb += self.dout.eq(rdport.data)
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with m.If(self.re & self.readable):
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if not self.fwft:
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m.d.sync += self.dout.eq(rdport.data)
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m.d.sync += consume.eq(rdport.addr)
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m.d[self.rdomain] += self.dout.eq(rdport.data)
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m.d[self.rdomain] += consume.eq(rdport.addr)
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m.d.comb += self.writable.eq(self.level < self.depth)
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m.d.comb += wrport.data.eq(self.din)
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@ -70,7 +83,7 @@ class FIFOModel(FIFOInterface):
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with m.If(~self.replace & self.writable):
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m.d.comb += wrport.addr.eq((produce + 1) % self.depth)
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m.d.comb += wrport.en.eq(1)
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m.d.sync += produce.eq(wrport.addr)
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m.d[self.wdomain] += produce.eq(wrport.addr)
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with m.If(self.replace):
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# The result of trying to replace an element in an empty queue is irrelevant.
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# The result of trying to replace the element that is currently being read
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@ -79,9 +92,14 @@ class FIFOModel(FIFOInterface):
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m.d.comb += wrport.addr.eq(produce)
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m.d.comb += wrport.en.eq(1)
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m.d.sync += self.level.eq(self.level
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+ (self.writable & self.we & ~self.replace)
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- (self.readable & self.re))
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with m.If(ResetSignal(self.rdomain) | ResetSignal(self.wdomain)):
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m.d.sync += self.level.eq(0)
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with m.Else():
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m.d.sync += self.level.eq(self.level
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+ (self.writable & self.we & ~self.replace)
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- (self.readable & self.re))
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m.d.comb += Assert(ResetSignal(self.rdomain) == ResetSignal(self.wdomain))
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return m.lower(platform)
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@ -92,13 +110,17 @@ class FIFOModelEquivalenceSpec:
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signals, the behavior of the implementation under test exactly matches the ideal model,
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except for behavior not defined by the model.
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"""
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def __init__(self, fifo):
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def __init__(self, fifo, rdomain, wdomain):
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self.fifo = fifo
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self.rdomain = rdomain
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self.wdomain = wdomain
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def get_fragment(self, platform):
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m = Module()
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m.submodules.dut = dut = self.fifo
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m.submodules.gold = gold = FIFOModel(dut.width, dut.depth, dut.fwft)
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m.submodules.gold = gold = FIFOModel(dut.width, dut.depth, dut.fwft,
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self.rdomain, self.wdomain)
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m.d.comb += [
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gold.re.eq(dut.readable & dut.re),
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@ -111,18 +133,18 @@ class FIFOModelEquivalenceSpec:
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m.d.comb += gold.replace.eq(0)
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m.d.comb += Assert(dut.readable.implies(gold.readable))
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m.d.comb += Assert(dut.writable.implies(gold.writable))
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if hasattr(dut, "level"):
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m.d.comb += Assert(dut.level == gold.level)
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if dut.fwft:
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m.d.comb += Assert(dut.readable
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.implies(dut.dout == gold.dout))
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else:
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m.d.comb += Assert((Past(dut.readable) & Past(dut.re))
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m.d.comb += Assert((Past(dut.readable, domain=self.rdomain) &
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Past(dut.re, domain=self.rdomain))
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.implies(dut.dout == gold.dout))
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m.d.comb += Assert(dut.writable == gold.writable)
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if hasattr(dut, "level"):
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m.d.comb += Assert(dut.level == gold.level)
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return m.lower(platform)
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@ -132,22 +154,32 @@ class FIFOContractSpec:
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consecutively, they must be read out consecutively at some later point, no matter all other
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circumstances, with the exception of reset.
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"""
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def __init__(self, fifo, bound):
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self.fifo = fifo
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self.bound = bound
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def __init__(self, fifo, rdomain, wdomain, bound):
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self.fifo = fifo
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self.rdomain = rdomain
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self.wdomain = wdomain
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self.bound = bound
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def get_fragment(self, platform):
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m = Module()
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m.submodules.dut = fifo = self.fifo
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m.domains += ClockDomain("sync")
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m.d.comb += ResetSignal().eq(0)
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if self.wdomain != "sync":
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m.domains += ClockDomain(self.wdomain)
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m.d.comb += ResetSignal(self.wdomain).eq(0)
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if self.rdomain != "sync":
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m.domains += ClockDomain(self.rdomain)
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m.d.comb += ResetSignal(self.rdomain).eq(0)
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if hasattr(fifo, "replace"):
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m.d.comb += fifo.replace.eq(0)
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entry_1 = AnyConst(fifo.width)
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entry_2 = AnyConst(fifo.width)
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with m.FSM() as write_fsm:
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with m.FSM(domain=self.wdomain) as write_fsm:
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with m.State("WRITE-1"):
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with m.If(fifo.writable):
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m.d.comb += [
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@ -163,12 +195,16 @@ class FIFOContractSpec:
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]
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m.next = "DONE"
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with m.FSM() as read_fsm:
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with m.FSM(domain=self.rdomain) as read_fsm:
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read_1 = Signal(fifo.width)
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read_2 = Signal(fifo.width)
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with m.State("READ"):
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m.d.comb += fifo.re.eq(1)
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with m.If(fifo.readable if fifo.fwft else Past(fifo.readable)):
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if fifo.fwft:
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readable = fifo.readable
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else:
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readable = Past(fifo.readable, domain=self.rdomain)
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with m.If(readable):
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m.d.sync += [
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read_1.eq(read_2),
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read_2.eq(fifo.dout),
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@ -184,33 +220,53 @@ class FIFOContractSpec:
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with m.If(Past(initstate, self.bound - 1)):
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m.d.comb += Assert(read_fsm.ongoing("DONE"))
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if self.wdomain != "sync" or self.rdomain != "sync":
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m.d.comb += Assume(Rose(ClockSignal(self.wdomain)) |
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Rose(ClockSignal(self.rdomain)))
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return m.lower(platform)
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class FIFOFormalCase(FHDLTestCase):
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def check_fifo(self, fifo):
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self.assertFormal(FIFOModelEquivalenceSpec(fifo),
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def check_sync_fifo(self, fifo):
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self.assertFormal(FIFOModelEquivalenceSpec(fifo, rdomain="sync", wdomain="sync"),
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mode="bmc", depth=fifo.depth + 1)
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self.assertFormal(FIFOContractSpec(fifo, bound=fifo.depth * 2 + 1),
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self.assertFormal(FIFOContractSpec(fifo, rdomain="sync", wdomain="sync",
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bound=fifo.depth * 2 + 1),
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mode="hybrid", depth=fifo.depth * 2 + 1)
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def test_sync_fwft_pot(self):
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self.check_fifo(SyncFIFO(width=8, depth=4, fwft=True))
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self.check_sync_fifo(SyncFIFO(width=8, depth=4, fwft=True))
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def test_sync_fwft_npot(self):
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self.check_fifo(SyncFIFO(width=8, depth=5, fwft=True))
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self.check_sync_fifo(SyncFIFO(width=8, depth=5, fwft=True))
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def test_sync_not_fwft_pot(self):
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self.check_fifo(SyncFIFO(width=8, depth=4, fwft=False))
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self.check_sync_fifo(SyncFIFO(width=8, depth=4, fwft=False))
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def test_sync_not_fwft_npot(self):
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self.check_fifo(SyncFIFO(width=8, depth=5, fwft=False))
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self.check_sync_fifo(SyncFIFO(width=8, depth=5, fwft=False))
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def test_sync_buffered_pot(self):
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self.check_fifo(SyncFIFOBuffered(width=8, depth=4))
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self.check_sync_fifo(SyncFIFOBuffered(width=8, depth=4))
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def test_sync_buffered_potp1(self):
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self.check_fifo(SyncFIFOBuffered(width=8, depth=5))
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self.check_sync_fifo(SyncFIFOBuffered(width=8, depth=5))
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def test_sync_buffered_potm1(self):
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self.check_fifo(SyncFIFOBuffered(width=8, depth=3))
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self.check_sync_fifo(SyncFIFOBuffered(width=8, depth=3))
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def check_async_fifo(self, fifo):
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# TODO: properly doing model equivalence checking on this likely requires multiclock,
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# which is not really documented nor is it clear how to use it.
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# self.assertFormal(FIFOModelEquivalenceSpec(fifo, rdomain="read", wdomain="write"),
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# mode="bmc", depth=fifo.depth * 3 + 1)
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self.assertFormal(FIFOContractSpec(fifo, rdomain="read", wdomain="write",
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bound=fifo.depth * 4 + 1),
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mode="hybrid", depth=fifo.depth * 4 + 1)
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def test_async(self):
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self.check_async_fifo(AsyncFIFO(width=8, depth=4))
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def test_async_buffered(self):
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self.check_async_fifo(AsyncFIFOBuffered(width=8, depth=3))
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