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back.pysim: delay clock processes by one half period.

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Makes it easier to see initial delta cycles.
This commit is contained in:
whitequark 2018-12-14 05:17:43 +00:00
parent 3bb7a87e0f
commit e4d08d2855
1 changed files with 1 additions and 0 deletions
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nmigen/back/pysim.py
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@ -231,6 +231,7 @@ class Simulator:
half_period = period / 2 half_period = period / 2
def clk_process(): def clk_process():
yield Passive() yield Passive()
yield Delay(half_period)
while True: while True:
yield clk.eq(1) yield clk.eq(1)
yield Delay(half_period) yield Delay(half_period)