back.pysim: delay clock processes by one half period.

Makes it easier to see initial delta cycles.
2018-12-14 05:17:43 +00:00 · 2018-12-14 05:17:43 +00:00 · e4d08d2855
parent 3bb7a87e0f
commit e4d08d2855
1 changed files with 1 additions and 0 deletions
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@ -231,6 +231,7 @@ class Simulator:
        half_period = period / 2
        def clk_process():
            yield Passive()
+            yield Delay(half_period)
            while True:
                yield clk.eq(1)
                yield Delay(half_period)