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hdl.{ast,dst}: directly represent RTLIL default case.

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This makes RTLIL mildly nicer:

 casez ({ \$5 , \$3 , \$1  })
   3'bzz1:
       \$next\o  = \$7 ;
   3'bz1z:
       \$next\o  = \$9 ;
   3'b1zz:
       \$next\o  = \$11 ;
-  3'bz:
+  default:
       { \$next\co , \$next\o  } = \$13 ;
 endcase
This commit is contained in:
whitequark 2019-06-25 17:53:09 +00:00
parent f60ceb349b
commit e5e23644a4
4 changed files with 20 additions and 14 deletions
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20
nmigen/back/pysim.py
View file

@ -319,16 +319,18 @@ class _StatementCompiler(StatementVisitor):
test = self.rrhs_compiler(stmt.test)
cases = []
for value, stmts in stmt.cases.items():
if "-" in value:
mask = "".join("0" if b == "-" else "1" for b in value)
value = "".join("0" if b == "-" else b for b in value)
if value is None:
check = lambda test: True
else:
mask = "1" * len(value)
mask = int(mask, 2)
value = int(value, 2)
def make_test(mask, value):
return lambda test: test & mask == value
cases.append((make_test(mask, value), self.on_statements(stmts)))
if "-" in value:
mask = "".join("0" if b == "-" else "1" for b in value)
value = "".join("0" if b == "-" else b for b in value)
else:
mask = "1" * len(value)
mask = int(mask, 2)
value = int(value, 2)
check = lambda test: test & mask == value
cases.append((check, self.on_statements(stmts)))
def run(state):
test_value = test(state)
for check, body in cases: