hdl.{ast,dst}: directly represent RTLIL default case.

This makes RTLIL mildly nicer:

 casez ({ \$5 , \$3 , \$1  })
   3'bzz1:
       \$next\o  = \$7 ;
   3'bz1z:
       \$next\o  = \$9 ;
   3'b1zz:
       \$next\o  = \$11 ;
-  3'bz:
+  default:
       { \$next\co , \$next\o  } = \$13 ;
 endcase

nmigen/hdl/ast.py

@@ -1024,10 +1024,12 @@ class Switch(Statement):
                 key = "{:0{}b}".format(key, len(self.test))
             elif isinstance(key, str):
                 pass
+            elif key is None:
+                pass
             else:
                 raise TypeError("Object '{!r}' cannot be used as a switch key"
                                 .format(key))
-            assert len(key) == len(self.test)
+            assert key is None or len(key) == len(self.test)
             if not isinstance(stmts, Iterable):
                 stmts = [stmts]
             self.cases[key] = Statement.wrap(stmts)
@@ -1043,7 +1045,9 @@ class Switch(Statement):
         return self.test._rhs_signals() | signals
 
     def __repr__(self):
-        cases = ["(case {} {})".format(key, " ".join(map(repr, stmts)))
+        cases = ["(default {})".format(" ".join(map(repr, stmts)))
+                 if key is None else
+                 "(case {} {})".format(key, " ".join(map(repr, stmts)))
                  for key, stmts in self.cases.items()]
         return "(switch {!r} {})".format(self.test, " ".join(cases))
 

nmigen/hdl/dsl.py

@@ -316,7 +316,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
                 if if_test is not None:
                     match = ("1" + "-" * (len(tests) - 1)).rjust(len(if_tests), "-")
                 else:
-                    match = "-" * len(tests)
+                    match = None
                 cases[match] = if_case
 
             self._statements.append(Switch(Cat(tests), cases))