compat.fhdl.decorators: port from oMigen.

nmigen/compat/__init__.py

@@ -2,7 +2,7 @@ from .fhdl.structure import *
 from .fhdl.module import *
 from .fhdl.specials import *
 from .fhdl.bitcontainer import *
-# from .fhdl.decorators import *
+from .fhdl.decorators import *
 # from .fhdl.simplify import *
 
 from .sim import *

nmigen/compat/fhdl/decorators.py

@@ -0,0 +1,41 @@
+from ...hdl.ast import *
+from ...hdl.xfrm import ResetInserter as NativeResetInserter
+from ...hdl.xfrm import CEInserter as NativeCEInserter
+from ...hdl.xfrm import DomainRenamer as NativeDomainRenamer
+
+
+__all__ = ["ResetInserter", "CEInserter", "ClockDomainsRenamer"]
+
+
+class _CompatControlInserter:
+    _control_name = None
+    _native_inserter = None
+
+    def __init__(self, clock_domains=None):
+        self.clock_domains = clock_domains
+
+    def __call__(self, module):
+        if self.clock_domains is None:
+            signals = {self._control_name: ("sync", Signal(name=self._control_name))}
+        else:
+            def name(cd):
+                return self._control_name + "_" + cd
+            signals = {name(cd): (cd, Signal(name=name(cd))) for cd in self.clock_domains}
+        for name, (cd, signal) in signals.items():
+            setattr(module, name, signal)
+        return self._native_inserter(dict(signals.values()))(module)
+
+
+class CompatResetInserter(_CompatControlInserter):
+    _control_name = "reset"
+    _native_inserter = NativeResetInserter
+
+
+class CompatCEInserter(_CompatControlInserter):
+    _control_name = "ce"
+    _native_inserter = NativeCEInserter
+
+
+ResetInserter = CompatResetInserter
+CEInserter = CompatCEInserter
+ClockDomainsRenamer = NativeDomainRenamer