back.rtlil: use slicing to match shape when reducing width.

nmigen/back/rtlil.py

@@ -339,19 +339,19 @@ class _RHSValueCompiler(_ValueCompiler):
             return self(ast.Const(value.value, (new_bits, new_sign)))
 
         value_bits, value_sign = value.shape()
-        if new_bits > value_bits:
+        if new_bits <= value_bits:
-            res = self.s.rtlil.wire(width=new_bits)
+            return self(ast.Slice(value, 0, new_bits))
-            self.s.rtlil.cell("$pos", ports={
+
-                "\\A": self(value),
+        res = self.s.rtlil.wire(width=new_bits)
-                "\\Y": res,
+        self.s.rtlil.cell("$pos", ports={
-            }, params={
+            "\\A": self(value),
-                "A_SIGNED": value_sign,
+            "\\Y": res,
-                "A_WIDTH": value_bits,
+        }, params={
-                "Y_WIDTH": new_bits,
+            "A_SIGNED": value_sign,
-            }, src=src(value.src_loc))
+            "A_WIDTH": value_bits,
-            return res
+            "Y_WIDTH": new_bits,
-        else:
+        }, src=src(value.src_loc))
-            return "{} [{}:0]".format(self(value), new_bits - 1)
+        return res
 
     def on_Operator_binary(self, value):
         lhs, rhs = value.operands