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back.rtlil: use slicing to match shape when reducing width.

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This commit is contained in:
whitequark 2018-12-16 16:20:45 +00:00
parent 2833b36c73
commit e86104d3a6
1 changed files with 13 additions and 13 deletions
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26
nmigen/back/rtlil.py
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@ -339,19 +339,19 @@ class _RHSValueCompiler(_ValueCompiler):
return self(ast.Const(value.value, (new_bits, new_sign)))
value_bits, value_sign = value.shape()
if new_bits > value_bits:
res = self.s.rtlil.wire(width=new_bits)
self.s.rtlil.cell("$pos", ports={
"\\A": self(value),
"\\Y": res,
}, params={
"A_SIGNED": value_sign,
"A_WIDTH": value_bits,
"Y_WIDTH": new_bits,
}, src=src(value.src_loc))
return res
else:
return "{} [{}:0]".format(self(value), new_bits - 1)
if new_bits <= value_bits:
return self(ast.Slice(value, 0, new_bits))
res = self.s.rtlil.wire(width=new_bits)
self.s.rtlil.cell("$pos", ports={
"\\A": self(value),
"\\Y": res,
}, params={
"A_SIGNED": value_sign,
"A_WIDTH": value_bits,
"Y_WIDTH": new_bits,
}, src=src(value.src_loc))
return res
def on_Operator_binary(self, value):
lhs, rhs = value.operands