hdl.ast: simplify Mux implementation.
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4 changed files with 9 additions and 4 deletions
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@ -542,7 +542,7 @@ class OperatorTestCase(FHDLTestCase):
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def test_mux_wide(self):
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s = Const(0b100)
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v = Mux(s, Const(0, unsigned(4)), Const(0, unsigned(6)))
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self.assertEqual(repr(v), "(m (b (const 3'd4)) (const 4'd0) (const 6'd0))")
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self.assertEqual(repr(v), "(m (const 3'd4) (const 4'd0) (const 6'd0))")
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def test_mux_bool(self):
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v = Mux(True, Const(0), Const(0))
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@ -191,6 +191,12 @@ class SimulatorUnitTestCase(FHDLTestCase):
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self.assertStatement(stmt, [C(2, 4), C(3, 4), C(0)], C(2, 4))
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self.assertStatement(stmt, [C(2, 4), C(3, 4), C(1)], C(3, 4))
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def test_mux_wide(self):
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stmt = lambda y, a, b, c: y.eq(Mux(c, a, b))
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self.assertStatement(stmt, [C(2, 4), C(3, 4), C(0, 2)], C(3, 4))
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self.assertStatement(stmt, [C(2, 4), C(3, 4), C(1, 2)], C(2, 4))
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self.assertStatement(stmt, [C(2, 4), C(3, 4), C(2, 2)], C(2, 4))
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def test_abs(self):
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stmt = lambda y, a: y.eq(abs(a))
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self.assertStatement(stmt, [C(3, unsigned(8))], C(3, unsigned(8)))
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