hdl.mem,lib,examples: use Signal.range().

examples/basic/fsm.py

@@ -15,7 +15,7 @@ class UARTReceiver(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        ctr = Signal(max=self.divisor)
+        ctr = Signal.range(self.divisor)
         stb = Signal()
         with m.If(ctr == 0):
             m.d.sync += ctr.eq(self.divisor - 1)

examples/basic/por.py

@@ -7,7 +7,7 @@ cd_por  = ClockDomain(reset_less=True)
 cd_sync = ClockDomain()
 m.domains += cd_por, cd_sync
 
-delay = Signal(max=255, reset=255)
+delay = Signal.range(256, reset=255)
 with m.If(delay != 0):
     m.d.por += delay.eq(delay - 1)
 m.d.comb += [

examples/basic/uart.py

@@ -31,9 +31,9 @@ class UART(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        tx_phase = Signal(max=self.divisor)
+        tx_phase = Signal.range(self.divisor)
         tx_shreg = Signal(1 + self.data_bits + 1, reset=-1)
-        tx_count = Signal(max=len(tx_shreg) + 1)
+        tx_count = Signal.range(len(tx_shreg) + 1)
 
         m.d.comb += self.tx_o.eq(tx_shreg[0])
         with m.If(tx_count == 0):
@@ -54,9 +54,9 @@ class UART(Elaboratable):
                     tx_phase.eq(self.divisor - 1),
                 ]
 
-        rx_phase = Signal(max=self.divisor)
+        rx_phase = Signal.range(self.divisor)
         rx_shreg = Signal(1 + self.data_bits + 1, reset=-1)
-        rx_count = Signal(max=len(rx_shreg) + 1)
+        rx_count = Signal.range(len(rx_shreg) + 1)
 
         m.d.comb += self.rx_data.eq(rx_shreg[1:-1])
         with m.If(rx_count == 0):