hdl.mem,lib,examples: use Signal.range().

nmigen/lib/coding.py

@@ -25,7 +25,7 @@ class Encoder(Elaboratable):
     ----------
     i : Signal(width), in
         One-hot input.
-    o : Signal(max=width), out
+    o : Signal.range(width), out
         Encoded binary.
     n : Signal, out
         Invalid: either none or multiple input bits are asserted.
@@ -34,7 +34,7 @@ class Encoder(Elaboratable):
         self.width = width
 
         self.i = Signal(width)
-        self.o = Signal(max=max(2, width))
+        self.o = Signal.range(width)
         self.n = Signal()
 
     def elaborate(self, platform):
@@ -64,7 +64,7 @@ class PriorityEncoder(Elaboratable):
     ----------
     i : Signal(width), in
         Input requests.
-    o : Signal(max=width), out
+    o : Signal.range(width), out
         Encoded binary.
     n : Signal, out
         Invalid: no input bits are asserted.
@@ -73,7 +73,7 @@ class PriorityEncoder(Elaboratable):
         self.width = width
 
         self.i = Signal(width)
-        self.o = Signal(max=max(2, width))
+        self.o = Signal.range(width)
         self.n = Signal()
 
     def elaborate(self, platform):
@@ -98,7 +98,7 @@ class Decoder(Elaboratable):
 
     Attributes
     ----------
-    i : Signal(max=width), in
+    i : Signal.range(width), in
         Input binary.
     o : Signal(width), out
         Decoded one-hot.
@@ -108,7 +108,7 @@ class Decoder(Elaboratable):
     def __init__(self, width):
         self.width = width
 
-        self.i = Signal(max=max(2, width))
+        self.i = Signal.range(width)
         self.n = Signal()
         self.o = Signal(width)
 

nmigen/lib/fifo.py

@@ -136,7 +136,7 @@ class SyncFIFO(Elaboratable, FIFOInterface):
     def __init__(self, width, depth, fwft=True):
         super().__init__(width, depth, fwft)
 
-        self.level   = Signal(max=depth + 1)
+        self.level   = Signal.range(depth + 1)
         self.replace = Signal()
 
     def elaborate(self, platform):
@@ -153,8 +153,8 @@ class SyncFIFO(Elaboratable, FIFOInterface):
         wrport  = m.submodules.wrport = storage.write_port()
         rdport  = m.submodules.rdport = storage.read_port(
             domain="comb" if self.fwft else "sync", transparent=self.fwft)
-        produce = Signal(max=self.depth)
-        consume = Signal(max=self.depth)
+        produce = Signal.range(self.depth)
+        consume = Signal.range(self.depth)
 
         m.d.comb += [
             wrport.addr.eq(produce),
@@ -234,7 +234,7 @@ class SyncFIFOBuffered(Elaboratable, FIFOInterface):
     def __init__(self, width, depth):
         super().__init__(width, depth, fwft=True)
 
-        self.level = Signal(max=depth + 1)
+        self.level = Signal.range(depth + 1)
 
     def elaborate(self, platform):
         m = Module()