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hdl.mem,lib,examples: use Signal.range().

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This commit is contained in:
whitequark 2019-09-08 12:19:13 +00:00
parent ccfbccc044
commit eb04a2509e
7 changed files with 21 additions and 21 deletions
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6
nmigen/test/test_lib_fifo.py
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@ -52,7 +52,7 @@ class FIFOModel(Elaboratable, FIFOInterface):
self.wdomain = wdomain
self.replace = Signal()
self.level = Signal(max=self.depth + 1)
self.level = Signal.range(self.depth + 1)
def elaborate(self, platform):
m = Module()
@ -61,8 +61,8 @@ class FIFOModel(Elaboratable, FIFOInterface):
wrport = m.submodules.wrport = storage.write_port(domain=self.wdomain)
rdport = m.submodules.rdport = storage.read_port (domain="comb")
produce = Signal(max=self.depth)
consume = Signal(max=self.depth)
produce = Signal.range(self.depth)
consume = Signal.range(self.depth)
m.d.comb += self.readable.eq(self.level > 0)
m.d.comb += rdport.addr.eq((consume + 1) % self.depth)