back.pysim: fix RHS codegen for Cat() and Repl(..., 0).

Fixes #325.
2020-02-19 01:21:00 +00:00 · 2020-02-19 01:21:00 +00:00 · ec7aee62ea
commit ec7aee62ea
parent 377f2d987d
2 changed files with 18 additions and 2 deletions
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@ -712,3 +712,15 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
            with sim.write_vcd(open(os.path.devnull, "wt")):
                with sim.write_vcd(open(os.path.devnull, "wt")):
                    pass
+
+
+class SimulatorRegressionTestCase(FHDLTestCase):
+    def test_bug_325(self):
+        dut = Module()
+        dut.d.comb += Signal().eq(Cat())
+        Simulator(dut).run()
+
+    def test_bug_325_bis(self):
+        dut = Module()
+        dut.d.comb += Signal().eq(Repl(Const(1), 0))
+        Simulator(dut).run()