compat.fhdl.module: allow adding native submodules to compat modules.

nmigen/compat/fhdl/module.py

@@ -61,12 +61,12 @@ class _CompatModuleSync(_CompatModuleProxy):
 class _CompatModuleSpecials(_CompatModuleProxy):
     @deprecated("instead of `self.specials.<name> =`, use `m.submodules.<name> =`")
     def __setattr__(self, name, value):
-        self._cm._specials.append((name, value))
+        self._cm._submodules.append((name, value))
         setattr(self._cm, name, value)
 
     @deprecated("instead of `self.specials +=`, use `m.submodules +=`")
     def __iadd__(self, other):
-        self._cm._specials += [(None, e) for e in _flat_list(other)]
+        self._cm._submodules += [(None, e) for e in _flat_list(other)]
         return self
 
 
@@ -135,14 +135,15 @@ class CompatModule:
             raise AttributeError("'{}' object has no attribute '{}'"
                                  .format(type(self).__name__, name))
 
-    def _finalize_specials(self):
-        for name, special in self._specials:
-            self._module._add_submodule(special, name)
-
     def _finalize_submodules(self):
         for name, submodule in self._submodules:
-            if not submodule.get_fragment_called:
+            if hasattr(submodule, "get_fragment_called"):
-                self._module._add_submodule(submodule.get_fragment(), name)
+                # Compat submodule
+                if not submodule.get_fragment_called:
+                    self._module._add_submodule(submodule.get_fragment(), name)
+            else:
+                # Native submodule
+                self._module._add_submodule(submodule, name)
 
     def finalize(self, *args, **kwargs):
         if not self.finalized:

nmigen/compat/fhdl/specials.py

@@ -1,10 +1,10 @@
-from ...genlib.io import TSTriple as NewTSTriple
+from ...genlib.io import TSTriple as NativeTSTriple
 
 
 __all__ = ["TSTriple"]
 
 
-class CompatTSTriple(NewTSTriple):
+class CompatTSTriple(NativeTSTriple):
     def __init__(self, bits_sign=None, min=None, max=None, reset_o=0, reset_oe=0, reset_i=0,
                  name=None):
         super().__init__(shape=bits_sign, min=min, max=max,

nmigen/fhdl/__init__.py

@@ -1,4 +1,5 @@
 from .cd import ClockDomain
 from .ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal
+from .ir import Fragment
 from .dsl import Module
 from .xfrm import ResetInserter, CEInserter