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back.rtlil: fix naming. NFC.

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This commit is contained in:
whitequark 2018-12-16 11:26:31 +00:00
parent 2be76fda3c
commit ed39748889
1 changed files with 64 additions and 64 deletions
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128
nmigen/back/rtlil.py
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@ -257,45 +257,45 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
finally: finally:
self.sub_name = None self.sub_name = None
def on_unknown(self, node): def on_unknown(self, value):
if node is None: if value is None:
return None return None
else: else:
super().visit_unknown(node) super().on_unknown(value)
def on_Const(self, node): def on_Const(self, value):
if isinstance(node.value, str): if isinstance(value.value, str):
return "{}'{}".format(node.nbits, node.value) return "{}'{}".format(value.nbits, value.value)
else: else:
return "{}'{:b}".format(node.nbits, node.value) return "{}'{:b}".format(value.nbits, value.value)
def on_Signal(self, node): def on_Signal(self, value):
if node in self.wires: if value in self.wires:
wire_curr, wire_next = self.wires[node] wire_curr, wire_next = self.wires[value]
else: else:
if node in self.ports: if value in self.ports:
port_id, port_kind = self.ports[node] port_id, port_kind = self.ports[value]
else: else:
port_id = port_kind = None port_id = port_kind = None
if self.sub_name: if self.sub_name:
wire_name = "{}_{}".format(self.sub_name, node.name) wire_name = "{}_{}".format(self.sub_name, value.name)
else: else:
wire_name = node.name wire_name = value.name
for attr_name, attr_value in node.attrs.items(): for attr_name, attr_value in value.attrs.items():
self.rtlil.attribute(attr_name, attr_value) self.rtlil.attribute(attr_name, attr_value)
wire_curr = self.rtlil.wire(width=node.nbits, name=wire_name, wire_curr = self.rtlil.wire(width=value.nbits, name=wire_name,
port_id=port_id, port_kind=port_kind, port_id=port_id, port_kind=port_kind,
src=src(node.src_loc)) src=src(value.src_loc))
if node in self.driven: if value in self.driven:
wire_next = self.rtlil.wire(width=node.nbits, name=wire_curr + "$next", wire_next = self.rtlil.wire(width=value.nbits, name=wire_curr + "$next",
src=src(node.src_loc)) src=src(value.src_loc))
else: else:
wire_next = None wire_next = None
self.wires[node] = (wire_curr, wire_next) self.wires[value] = (wire_curr, wire_next)
if self.is_lhs: if self.is_lhs:
if wire_next is None: if wire_next is None:
raise ValueError("Cannot return lhs for non-driven signal {}".format(repr(node))) raise ValueError("Cannot return lhs for non-driven signal {}".format(repr(value)))
return wire_next return wire_next
else: else:
return wire_curr return wire_curr
@ -306,42 +306,42 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
def on_ResetSignal(self, value): def on_ResetSignal(self, value):
raise NotImplementedError # :nocov: raise NotImplementedError # :nocov:
def on_Operator_unary(self, node): def on_Operator_unary(self, value):
arg, = node.operands arg, = value.operands
arg_bits, arg_sign = arg.shape() arg_bits, arg_sign = arg.shape()
res_bits, res_sign = node.shape() res_bits, res_sign = value.shape()
res = self.rtlil.wire(width=res_bits) res = self.rtlil.wire(width=res_bits)
self.rtlil.cell(self.operator_map[(1, node.op)], ports={ self.rtlil.cell(self.operator_map[(1, value.op)], ports={
"\\A": self(arg), "\\A": self(arg),
"\\Y": res, "\\Y": res,
}, params={ }, params={
"A_SIGNED": arg_sign, "A_SIGNED": arg_sign,
"A_WIDTH": arg_bits, "A_WIDTH": arg_bits,
"Y_WIDTH": res_bits, "Y_WIDTH": res_bits,
}, src=src(node.src_loc)) }, src=src(value.src_loc))
return res return res
def match_shape(self, node, new_bits, new_sign): def match_shape(self, value, new_bits, new_sign):
if isinstance(node, ast.Const): if isinstance(value, ast.Const):
return self(ast.Const(node.value, (new_bits, new_sign))) return self(ast.Const(value.value, (new_bits, new_sign)))
node_bits, node_sign = node.shape() value_bits, value_sign = value.shape()
if new_bits > node_bits: if new_bits > value_bits:
res = self.rtlil.wire(width=new_bits) res = self.rtlil.wire(width=new_bits)
self.rtlil.cell("$pos", ports={ self.rtlil.cell("$pos", ports={
"\\A": self(node), "\\A": self(value),
"\\Y": res, "\\Y": res,
}, params={ }, params={
"A_SIGNED": node_sign, "A_SIGNED": value_sign,
"A_WIDTH": node_bits, "A_WIDTH": value_bits,
"Y_WIDTH": new_bits, "Y_WIDTH": new_bits,
}, src=src(node.src_loc)) }, src=src(value.src_loc))
return res return res
else: else:
return "{} [{}:0]".format(self(node), new_bits - 1) return "{} [{}:0]".format(self(value), new_bits - 1)
def on_Operator_binary(self, node): def on_Operator_binary(self, value):
lhs, rhs = node.operands lhs, rhs = value.operands
lhs_bits, lhs_sign = lhs.shape() lhs_bits, lhs_sign = lhs.shape()
rhs_bits, rhs_sign = rhs.shape() rhs_bits, rhs_sign = rhs.shape()
if lhs_sign == rhs_sign: if lhs_sign == rhs_sign:
@ -352,9 +352,9 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
lhs_bits = rhs_bits = max(lhs_bits, rhs_bits) lhs_bits = rhs_bits = max(lhs_bits, rhs_bits)
lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign) lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign) rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
res_bits, res_sign = node.shape() res_bits, res_sign = value.shape()
res = self.rtlil.wire(width=res_bits) res = self.rtlil.wire(width=res_bits)
self.rtlil.cell(self.operator_map[(2, node.op)], ports={ self.rtlil.cell(self.operator_map[(2, value.op)], ports={
"\\A": lhs_wire, "\\A": lhs_wire,
"\\B": rhs_wire, "\\B": rhs_wire,
"\\Y": res, "\\Y": res,
@ -364,14 +364,14 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
"B_SIGNED": rhs_sign, "B_SIGNED": rhs_sign,
"B_WIDTH": rhs_bits, "B_WIDTH": rhs_bits,
"Y_WIDTH": res_bits, "Y_WIDTH": res_bits,
}, src=src(node.src_loc)) }, src=src(value.src_loc))
return res return res
def on_Operator_mux(self, node): def on_Operator_mux(self, value):
sel, lhs, rhs = node.operands sel, lhs, rhs = value.operands
lhs_bits, lhs_sign = lhs.shape() lhs_bits, lhs_sign = lhs.shape()
rhs_bits, rhs_sign = rhs.shape() rhs_bits, rhs_sign = rhs.shape()
res_bits, res_sign = node.shape() res_bits, res_sign = value.shape()
lhs_bits = rhs_bits = res_bits = max(lhs_bits, rhs_bits, res_bits) lhs_bits = rhs_bits = res_bits = max(lhs_bits, rhs_bits, res_bits)
lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign) lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign) rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
@ -383,36 +383,36 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
"\\Y": res, "\\Y": res,
}, params={ }, params={
"WIDTH": res_bits "WIDTH": res_bits
}, src=src(node.src_loc)) }, src=src(value.src_loc))
return res return res
def on_Operator(self, node): def on_Operator(self, value):
if len(node.operands) == 1: if len(value.operands) == 1:
return self.on_Operator_unary(node) return self.on_Operator_unary(value)
elif len(node.operands) == 2: elif len(value.operands) == 2:
return self.on_Operator_binary(node) return self.on_Operator_binary(value)
elif len(node.operands) == 3: elif len(value.operands) == 3:
assert node.op == "m" assert value.op == "m"
return self.on_Operator_mux(node) return self.on_Operator_mux(value)
else: else:
raise TypeError raise TypeError
def on_Slice(self, node): def on_Slice(self, value):
if node.end == node.start + 1: if value.end == value.start + 1:
return "{} [{}]".format(self(node.value), node.start) return "{} [{}]".format(self(value.value), value.start)
else: else:
return "{} [{}:{}]".format(self(node.value), node.end - 1, node.start) return "{} [{}:{}]".format(self(value.value), value.end - 1, value.start)
def on_Part(self, node): def on_Part(self, value):
raise NotImplementedError raise NotImplementedError
def on_Cat(self, node): def on_Cat(self, value):
return "{{ {} }}".format(" ".join(reversed([self(o) for o in node.operands]))) return "{{ {} }}".format(" ".join(reversed([self(o) for o in value.operands])))
def on_Repl(self, node): def on_Repl(self, value):
return "{{ {} }}".format(" ".join(self(node.value) for _ in range(node.count))) return "{{ {} }}".format(" ".join(self(value.value) for _ in range(value.count)))
def on_ArrayProxy(self, node): def on_ArrayProxy(self, value):
raise NotImplementedError raise NotImplementedError