back.rtlil: fix naming. NFC.
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whitequark
parent
2be76fda3c
commit
ed39748889
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@ -257,45 +257,45 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
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finally:
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self.sub_name = None
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def on_unknown(self, node):
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if node is None:
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def on_unknown(self, value):
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if value is None:
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return None
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else:
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super().visit_unknown(node)
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super().on_unknown(value)
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def on_Const(self, node):
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if isinstance(node.value, str):
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return "{}'{}".format(node.nbits, node.value)
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def on_Const(self, value):
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if isinstance(value.value, str):
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return "{}'{}".format(value.nbits, value.value)
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else:
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return "{}'{:b}".format(node.nbits, node.value)
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return "{}'{:b}".format(value.nbits, value.value)
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def on_Signal(self, node):
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if node in self.wires:
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wire_curr, wire_next = self.wires[node]
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def on_Signal(self, value):
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if value in self.wires:
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wire_curr, wire_next = self.wires[value]
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else:
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if node in self.ports:
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port_id, port_kind = self.ports[node]
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if value in self.ports:
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port_id, port_kind = self.ports[value]
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else:
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port_id = port_kind = None
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if self.sub_name:
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wire_name = "{}_{}".format(self.sub_name, node.name)
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wire_name = "{}_{}".format(self.sub_name, value.name)
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else:
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wire_name = node.name
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for attr_name, attr_value in node.attrs.items():
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wire_name = value.name
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for attr_name, attr_value in value.attrs.items():
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self.rtlil.attribute(attr_name, attr_value)
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wire_curr = self.rtlil.wire(width=node.nbits, name=wire_name,
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wire_curr = self.rtlil.wire(width=value.nbits, name=wire_name,
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port_id=port_id, port_kind=port_kind,
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src=src(node.src_loc))
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if node in self.driven:
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wire_next = self.rtlil.wire(width=node.nbits, name=wire_curr + "$next",
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src=src(node.src_loc))
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src=src(value.src_loc))
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if value in self.driven:
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wire_next = self.rtlil.wire(width=value.nbits, name=wire_curr + "$next",
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src=src(value.src_loc))
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else:
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wire_next = None
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self.wires[node] = (wire_curr, wire_next)
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self.wires[value] = (wire_curr, wire_next)
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if self.is_lhs:
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if wire_next is None:
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raise ValueError("Cannot return lhs for non-driven signal {}".format(repr(node)))
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raise ValueError("Cannot return lhs for non-driven signal {}".format(repr(value)))
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return wire_next
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else:
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return wire_curr
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@ -306,42 +306,42 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
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def on_ResetSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_Operator_unary(self, node):
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arg, = node.operands
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def on_Operator_unary(self, value):
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arg, = value.operands
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arg_bits, arg_sign = arg.shape()
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res_bits, res_sign = node.shape()
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res_bits, res_sign = value.shape()
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res = self.rtlil.wire(width=res_bits)
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self.rtlil.cell(self.operator_map[(1, node.op)], ports={
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self.rtlil.cell(self.operator_map[(1, value.op)], ports={
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"\\A": self(arg),
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"\\Y": res,
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}, params={
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"A_SIGNED": arg_sign,
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"A_WIDTH": arg_bits,
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"Y_WIDTH": res_bits,
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}, src=src(node.src_loc))
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}, src=src(value.src_loc))
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return res
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def match_shape(self, node, new_bits, new_sign):
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if isinstance(node, ast.Const):
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return self(ast.Const(node.value, (new_bits, new_sign)))
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def match_shape(self, value, new_bits, new_sign):
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if isinstance(value, ast.Const):
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return self(ast.Const(value.value, (new_bits, new_sign)))
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node_bits, node_sign = node.shape()
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if new_bits > node_bits:
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value_bits, value_sign = value.shape()
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if new_bits > value_bits:
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res = self.rtlil.wire(width=new_bits)
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self.rtlil.cell("$pos", ports={
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"\\A": self(node),
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"\\A": self(value),
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"\\Y": res,
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}, params={
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"A_SIGNED": node_sign,
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"A_WIDTH": node_bits,
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"A_SIGNED": value_sign,
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"A_WIDTH": value_bits,
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"Y_WIDTH": new_bits,
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}, src=src(node.src_loc))
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}, src=src(value.src_loc))
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return res
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else:
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return "{} [{}:0]".format(self(node), new_bits - 1)
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return "{} [{}:0]".format(self(value), new_bits - 1)
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def on_Operator_binary(self, node):
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lhs, rhs = node.operands
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def on_Operator_binary(self, value):
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lhs, rhs = value.operands
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lhs_bits, lhs_sign = lhs.shape()
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rhs_bits, rhs_sign = rhs.shape()
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if lhs_sign == rhs_sign:
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@ -352,9 +352,9 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
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lhs_bits = rhs_bits = max(lhs_bits, rhs_bits)
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lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
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rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
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res_bits, res_sign = node.shape()
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res_bits, res_sign = value.shape()
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res = self.rtlil.wire(width=res_bits)
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self.rtlil.cell(self.operator_map[(2, node.op)], ports={
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self.rtlil.cell(self.operator_map[(2, value.op)], ports={
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"\\A": lhs_wire,
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"\\B": rhs_wire,
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"\\Y": res,
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@ -364,14 +364,14 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
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"B_SIGNED": rhs_sign,
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"B_WIDTH": rhs_bits,
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"Y_WIDTH": res_bits,
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}, src=src(node.src_loc))
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}, src=src(value.src_loc))
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return res
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def on_Operator_mux(self, node):
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sel, lhs, rhs = node.operands
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def on_Operator_mux(self, value):
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sel, lhs, rhs = value.operands
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lhs_bits, lhs_sign = lhs.shape()
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rhs_bits, rhs_sign = rhs.shape()
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res_bits, res_sign = node.shape()
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res_bits, res_sign = value.shape()
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lhs_bits = rhs_bits = res_bits = max(lhs_bits, rhs_bits, res_bits)
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lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
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rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
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@ -383,36 +383,36 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
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"\\Y": res,
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}, params={
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"WIDTH": res_bits
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}, src=src(node.src_loc))
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}, src=src(value.src_loc))
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return res
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def on_Operator(self, node):
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if len(node.operands) == 1:
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return self.on_Operator_unary(node)
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elif len(node.operands) == 2:
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return self.on_Operator_binary(node)
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elif len(node.operands) == 3:
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assert node.op == "m"
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return self.on_Operator_mux(node)
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def on_Operator(self, value):
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if len(value.operands) == 1:
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return self.on_Operator_unary(value)
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elif len(value.operands) == 2:
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return self.on_Operator_binary(value)
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elif len(value.operands) == 3:
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assert value.op == "m"
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return self.on_Operator_mux(value)
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else:
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raise TypeError
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def on_Slice(self, node):
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if node.end == node.start + 1:
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return "{} [{}]".format(self(node.value), node.start)
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def on_Slice(self, value):
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if value.end == value.start + 1:
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return "{} [{}]".format(self(value.value), value.start)
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else:
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return "{} [{}:{}]".format(self(node.value), node.end - 1, node.start)
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return "{} [{}:{}]".format(self(value.value), value.end - 1, value.start)
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def on_Part(self, node):
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def on_Part(self, value):
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raise NotImplementedError
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def on_Cat(self, node):
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return "{{ {} }}".format(" ".join(reversed([self(o) for o in node.operands])))
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def on_Cat(self, value):
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return "{{ {} }}".format(" ".join(reversed([self(o) for o in value.operands])))
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def on_Repl(self, node):
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return "{{ {} }}".format(" ".join(self(node.value) for _ in range(node.count)))
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def on_Repl(self, value):
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return "{{ {} }}".format(" ".join(self(value.value) for _ in range(value.count)))
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def on_ArrayProxy(self, node):
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def on_ArrayProxy(self, value):
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raise NotImplementedError
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