usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

build.{plat,res}: add support for connectors.

Browse source 
Fixes #77.
This commit is contained in:
whitequark 2019-06-03 15:02:15 +00:00
parent a013eb1f59
commit ed64880cc4
4 changed files with 95 additions and 44 deletions
Download patch file Download diff file Expand all files Collapse all files

24
nmigen/vendor/fpga/lattice_ice40.py vendored
View file

@ -109,11 +109,11 @@ class LatticeICE40Platform(TemplatedPlatform):
]
def iter_ports(self):
for resource, pin, port in self._ports:
if isinstance(resource.io[0], Pins):
for res, pin, port in self._ports:
if isinstance(res.io[0], Pins):
yield port.io
elif isinstance(resource.io[0], DiffPairs):
if resource.extras.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT":
elif isinstance(res.io[0], DiffPairs):
if res.extras.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT":
yield port.p
else:
yield port.p
@ -122,15 +122,15 @@ class LatticeICE40Platform(TemplatedPlatform):
assert False
def iter_port_constraints(self):
for resource, pin, port in self._ports:
if isinstance(resource.io[0], Pins):
yield port.io.name, resource.io[0].names, resource.extras
elif isinstance(resource.io[0], DiffPairs):
if resource.extras.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT":
yield port.p.name, resource.io[0].p.names, resource.extras
for res, pin, port in self._ports:
if isinstance(res.io[0], Pins):
yield port.io.name, list(res.io[0].map_names(self._mapping, res)), res.extras
elif isinstance(res.io[0], DiffPairs):
if res.extras.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT":
yield port.p.name, list(res.io[0].p.map_names(self._mapping, res)), res.extras
else:
yield port.p.name, resource.io[0].p.names, resource.extras
yield port.n.name, resource.io[0].n.names, resource.extras
yield port.p.name, list(res.io[0].p.map_names(self._mapping, res)), res.extras
yield port.n.name, list(res.io[0].n.map_names(self._mapping, res)), res.extras
else:
assert False