usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

hdl.ast: implement Initial.

Browse source 
This is the last remaining part for first-class formal support.
This commit is contained in:
whitequark 2019-08-15 02:53:07 +00:00
parent 40abaef858
commit ed7e07c6c1
8 changed files with 68 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

9
nmigen/lib/fifo.py
View file

@ -181,9 +181,7 @@ class SyncFIFO(Elaboratable, FIFOInterface):
if platform == "formal":
# TODO: move this logic to SymbiYosys
initstate = Signal()
m.submodules += Instance("$initstate", o_Y=initstate)
with m.If(initstate):
with m.If(Initial()):
m.d.comb += [
Assume(produce < self.depth),
Assume(consume < self.depth),
@ -351,10 +349,7 @@ class AsyncFIFO(Elaboratable, FIFOInterface):
]
if platform == "formal":
# TODO: move this logic elsewhere
initstate = Signal()
m.submodules += Instance("$initstate", o_Y=initstate)
with m.If(initstate):
with m.If(Initial()):
m.d.comb += Assume(produce_w_gry == (produce_w_bin ^ produce_w_bin[1:]))
m.d.comb += Assume(consume_r_gry == (consume_r_bin ^ consume_r_bin[1:]))