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hdl.ast: implement Initial.

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This is the last remaining part for first-class formal support.
This commit is contained in:
whitequark 2019-08-15 02:53:07 +00:00
parent 40abaef858
commit ed7e07c6c1
8 changed files with 68 additions and 16 deletions
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6
nmigen/test/test_hdl_ast.py
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@ -614,3 +614,9 @@ class SampleTestCase(FHDLTestCase):
with self.assertRaises(ValueError,
"Cannot sample a value 1 cycles in the future"):
Sample(Signal(), -1, "sync")
class InitialTestCase(FHDLTestCase):
def test_initial(self):
i = Initial()
self.assertEqual(i.shape(), (1, False))

6
nmigen/test/test_lib_fifo.py
View file

@ -208,12 +208,10 @@ class FIFOContractSpec(Elaboratable):
with m.If((read_1 == entry_1) & (read_2 == entry_2)):
m.next = "DONE"
initstate = Signal()
m.submodules += Instance("$initstate", o_Y=initstate)
with m.If(initstate):
with m.If(Initial()):
m.d.comb += Assume(write_fsm.ongoing("WRITE-1"))
m.d.comb += Assume(read_fsm.ongoing("READ"))
with m.If(Past(initstate, self.bound - 1)):
with m.If(Past(Initial(), self.bound - 1)):
m.d.comb += Assert(read_fsm.ongoing("DONE"))
if self.wdomain != "sync" or self.rdomain != "sync":