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compat.fhdl.specials: use "sync" as default domain, not "sys".

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In compat.fhdl.module, we already default to "sync" as the default
clocked domain. Using "sys" in memories only would be inconsistent
and result in more bugs.
This commit is contained in:
whitequark 2019-07-03 13:25:12 +00:00
parent c98b8f7c07
commit eeb6aca93d
1 changed files with 2 additions and 2 deletions
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4
nmigen/compat/fhdl/specials.py
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@ -65,7 +65,7 @@ class Tristate(Elaboratable):
class _MemoryPort(CompatModule): class _MemoryPort(CompatModule):
def __init__(self, adr, dat_r, we=None, dat_w=None, async_read=False, re=None, def __init__(self, adr, dat_r, we=None, dat_w=None, async_read=False, re=None,
we_granularity=0, mode=WRITE_FIRST, clock_domain="sys"): we_granularity=0, mode=WRITE_FIRST, clock_domain="sync"):
self.adr = adr self.adr = adr
self.dat_r = dat_r self.dat_r = dat_r
self.we = we self.we = we
@ -86,7 +86,7 @@ def elaborate(self, platform):
class CompatMemory(NativeMemory): class CompatMemory(NativeMemory):
@deprecated("instead of `get_port()`, use `read_port()` and `write_port()`") @deprecated("instead of `get_port()`, use `read_port()` and `write_port()`")
def get_port(self, write_capable=False, async_read=False, has_re=False, we_granularity=0, def get_port(self, write_capable=False, async_read=False, has_re=False, we_granularity=0,
mode=WRITE_FIRST, clock_domain="sys"): mode=WRITE_FIRST, clock_domain="sync"):
if we_granularity >= self.width: if we_granularity >= self.width:
warnings.warn("do not specify `we_granularity` greater than memory width, as it " warnings.warn("do not specify `we_granularity` greater than memory width, as it "
"is a hard error in non-compatibility mode", "is a hard error in non-compatibility mode",