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build.{dsl,res,plat}: add PinsN and DiffPairsN.

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This commit is contained in:
whitequark 2019-06-12 14:42:39 +00:00
parent ad1a40c934
commit efb2d773c3
8 changed files with 169 additions and 77 deletions
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13
nmigen/test/test_build_dsl.py
View file

@ -10,8 +10,14 @@ class PinsTestCase(FHDLTestCase):
self.assertEqual(repr(p), "(pins io A0 A1 A2)")
self.assertEqual(len(p.names), 3)
self.assertEqual(p.dir, "io")
self.assertEqual(p.invert, False)
self.assertEqual(list(p), ["A0", "A1", "A2"])
def test_invert(self):
p = PinsN("A0")
self.assertEqual(repr(p), "(pins-n io A0)")
self.assertEqual(p.invert, True)
def test_conn(self):
p = Pins("0 1 2", conn=("pmod", 0))
self.assertEqual(list(p), ["pmod_0:0", "pmod_0:1", "pmod_0:2"])
@ -63,6 +69,13 @@ class DiffPairsTestCase(FHDLTestCase):
self.assertEqual(dp.dir, "io")
self.assertEqual(list(dp), [("A0", "B0"), ("A1", "B1")])
def test_invert(self):
dp = DiffPairsN(p="A0", n="B0")
self.assertEqual(repr(dp), "(diffpairs-n io (p A0) (n B0))")
self.assertEqual(dp.p.names, ["A0"])
self.assertEqual(dp.n.names, ["B0"])
self.assertEqual(dp.invert, True)
def test_conn(self):
dp = DiffPairs(p="0 1 2", n="3 4 5", conn=("pmod", 0))
self.assertEqual(list(dp), [

23
nmigen/test/test_build_res.py
View file

@ -84,8 +84,8 @@ class ResourceManagerTestCase(FHDLTestCase):
self.assertEqual(ports[1].nbits, 1)
self.assertEqual(list(self.cm.iter_single_ended_pins()), [
(i2c.scl, scl, {}),
(i2c.sda, sda, {}),
(i2c.scl, scl, {}, False),
(i2c.sda, sda, {}, False),
])
self.assertEqual(list(self.cm.iter_port_constraints()), [
("i2c_0__scl__io", ["N10"], {}),
@ -107,13 +107,30 @@ class ResourceManagerTestCase(FHDLTestCase):
self.assertEqual(n.nbits, clk100.width)
self.assertEqual(list(self.cm.iter_differential_pins()), [
(clk100, p, n, {}),
(clk100, p, n, {}, False),
])
self.assertEqual(list(self.cm.iter_port_constraints()), [
("clk100_0__p", ["H1"], {}),
("clk100_0__n", ["H2"], {}),
])
def test_request_inverted(self):
new_resources = [
Resource("cs", 0, PinsN("X0")),
Resource("clk", 0, DiffPairsN("Y0", "Y1")),
]
self.cm.add_resources(new_resources)
sig_cs = self.cm.request("cs")
sig_clk = self.cm.request("clk")
port_cs, port_clk_p, port_clk_n = self.cm.iter_ports()
self.assertEqual(list(self.cm.iter_single_ended_pins()), [
(sig_cs, port_cs, {}, True),
])
self.assertEqual(list(self.cm.iter_differential_pins()), [
(sig_clk, port_clk_p, port_clk_n, {}, True),
])
def test_request_raw(self):
clk50 = self.cm.request("clk50", 0, dir="-")
self.assertIsInstance(clk50, Record)