build.{dsl,res,plat}: add PinsN and DiffPairsN.
This commit is contained in:
whitequark
parent
ad1a40c934
commit
efb2d773c3
8 changed files with 169 additions and 77 deletions
76
nmigen/vendor/lattice_ice40.py
vendored
76
nmigen/vendor/lattice_ice40.py
vendored
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@ -120,8 +120,8 @@ class LatticeICE40Platform(TemplatedPlatform):
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return True
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return False
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def _get_io_buffer(self, m, pin, port, attrs, o_invert=None):
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def _get_dff(clk, d, q):
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def _get_io_buffer(self, m, pin, port, attrs, i_invert=None, o_invert=None):
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def get_dff(clk, d, q):
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m.submodules += Instance("$dff",
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p_CLK_POLARITY=0,
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p_WIDTH=len(d),
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@ -129,7 +129,22 @@ class LatticeICE40Platform(TemplatedPlatform):
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i_D=d,
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o_Q=q)
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def _get_inverter(a, invert):
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def get_i_inverter(y, invert):
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if invert is None:
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return y
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else:
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a = Signal.like(y, name="{}_x{}".format(a.name, 1 if invert else 0))
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for bit in range(len(y)):
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m.submodules += Instance("SB_LUT4",
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p_LUT_INIT=0b01 if invert else 0b10,
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i_I0=a[bit],
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i_I1=Const(0),
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i_I2=Const(0),
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i_I3=Const(0),
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o_O=y[bit])
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return a
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def get_o_inverter(a, invert):
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if invert is None:
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return a
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else:
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@ -150,21 +165,27 @@ class LatticeICE40Platform(TemplatedPlatform):
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else:
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is_global_input = False
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if "i" in pin.dir:
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if pin.xdr < 2:
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pin_i = get_i_inverter(pin.i, i_invert)
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elif pin.xdr == 2:
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pin_i0 = get_i_inverter(pin.i0, i_invert)
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pin_i1 = get_i_inverter(pin.i1, i_invert)
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if "o" in pin.dir:
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if pin.xdr < 2:
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pin_o = _get_inverter(pin.o, o_invert)
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pin_o = get_o_inverter(pin.o, o_invert)
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elif pin.xdr == 2:
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pin_o0 = _get_inverter(pin.o0, o_invert)
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pin_o1 = _get_inverter(pin.o1, o_invert)
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pin_o0 = get_o_inverter(pin.o0, o_invert)
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pin_o1 = get_o_inverter(pin.o1, o_invert)
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if "i" in pin.dir and pin.xdr == 2:
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i0_ff = Signal.like(pin.i0, name="{}_ff".format(pin.i0.name))
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i1_ff = Signal.like(pin.i1, name="{}_ff".format(pin.i1.name))
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_get_dff(pin.i_clk, i0_ff, pin.i0)
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_get_dff(pin.i_clk, i1_ff, pin.i1)
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i0_ff = Signal.like(pin_i0, name="{}_ff".format(pin_i0.name))
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i1_ff = Signal.like(pin_i1, name="{}_ff".format(pin_i1.name))
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get_dff(pin.i_clk, i0_ff, pin_i0)
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get_dff(pin.i_clk, i1_ff, pin_i1)
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if "o" in pin.dir and pin.xdr == 2:
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o1_ff = Signal.like(pin.o1, name="{}_ff".format(pin.o1.name))
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_get_dff(pin.o_clk, pin_o1, o1_ff)
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o1_ff = Signal.like(pin_o1, name="{}_ff".format(pin_o1.name))
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get_dff(pin.o_clk, pin_o1, o1_ff)
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for bit in range(len(port)):
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io_args = [
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@ -201,9 +222,9 @@ class LatticeICE40Platform(TemplatedPlatform):
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if "i" in pin.dir:
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if pin.xdr == 0 and is_global_input:
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io_args.append(("o", "GLOBAL_BUFFER_OUTPUT", pin.i[bit]))
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io_args.append(("o", "GLOBAL_BUFFER_OUTPUT", pin_i[bit]))
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elif pin.xdr < 2:
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io_args.append(("o", "D_IN_0", pin.i[bit]))
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io_args.append(("o", "D_IN_0", pin_i[bit]))
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elif pin.xdr == 2:
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# Re-register both inputs before they enter fabric. This increases hold time
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# to an entire cycle, and adds one cycle of latency.
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@ -226,43 +247,44 @@ class LatticeICE40Platform(TemplatedPlatform):
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else:
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m.submodules += Instance("SB_IO", *io_args)
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def get_input(self, pin, port, attrs):
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def get_input(self, pin, port, attrs, invert):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, port, attrs)
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self._get_io_buffer(m, pin, port, attrs, i_invert=True if invert else None)
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return m
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def get_output(self, pin, port, attrs):
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def get_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, port, attrs)
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self._get_io_buffer(m, pin, port, attrs, o_invert=True if invert else None)
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return m
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def get_tristate(self, pin, port, attrs):
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def get_tristate(self, pin, port, attrs, invert):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, port, attrs)
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self._get_io_buffer(m, pin, port, attrs, o_invert=True if invert else None)
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return m
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def get_input_output(self, pin, port, attrs):
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def get_input_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, port, attrs)
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self._get_io_buffer(m, pin, port, attrs, i_invert=True if invert else None,
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o_invert=True if invert else None)
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return m
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def get_diff_input(self, pin, p_port, n_port, attrs):
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def get_diff_input(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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# See comment in should_skip_port_component above.
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self._get_io_buffer(m, pin, p_port, attrs)
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self._get_io_buffer(m, pin, p_port, attrs, i_invert=True if invert else None)
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return m
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def get_diff_output(self, pin, p_port, n_port, attrs):
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def get_diff_output(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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@ -270,8 +292,8 @@ class LatticeICE40Platform(TemplatedPlatform):
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# output pin. The inverter introduces a delay, so for a non-inverting output pin,
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# an identical delay is introduced by instantiating a LUT. This makes the waveform
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# perfectly symmetric in the xdr=0 case.
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self._get_io_buffer(m, pin, p_port, attrs, o_invert=False)
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self._get_io_buffer(m, pin, n_port, attrs, o_invert=True)
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self._get_io_buffer(m, pin, p_port, attrs, o_invert=invert)
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self._get_io_buffer(m, pin, n_port, attrs, o_invert=not invert)
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return m
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# Tristate and bidirectional buffers are not supported on iCE40 because it requires external
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24
nmigen/vendor/xilinx_7series.py
vendored
24
nmigen/vendor/xilinx_7series.py
vendored
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@ -129,7 +129,8 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
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)
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m.d.comb += q[bit].eq(_q)
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def get_input(self, pin, port, attrs):
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def get_input(self, pin, port, attrs, invert):
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assert not invert
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -139,7 +140,8 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
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m.d.comb += pin.i.eq(port)
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return m
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def get_output(self, pin, port, attrs):
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def get_output(self, pin, port, attrs, invert):
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assert not invert
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -149,7 +151,8 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
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m.d.comb += port.eq(pin.o)
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return m
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def get_tristate(self, pin, port, attrs):
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def get_tristate(self, pin, port, attrs, invert):
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assert not invert
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -166,7 +169,8 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
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)
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return m
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def get_input_output(self, pin, port, attrs):
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def get_input_output(self, pin, port, attrs, invert):
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assert not invert
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -186,7 +190,8 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
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)
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return m
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def get_diff_input(self, pin, p_port, n_port, attrs):
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def get_diff_input(self, pin, p_port, n_port, attrs, invert):
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assert not invert
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -201,7 +206,8 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
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)
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return m
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def get_diff_output(self, pin, p_port, n_port, attrs):
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def get_diff_output(self, pin, p_port, n_port, attrs, invert):
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assert not invert
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -216,7 +222,8 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
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)
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return m
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def get_diff_tristate(self, pin, p_port, n_port, attrs):
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def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
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assert not invert
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -234,7 +241,8 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
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)
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return m
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def get_diff_input_output(self, pin, p_port, n_port, attrs):
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def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
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assert not invert
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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24
nmigen/vendor/xilinx_spartan6.py
vendored
24
nmigen/vendor/xilinx_spartan6.py
vendored
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@ -140,7 +140,8 @@ class XilinxSpartan6Platform(TemplatedPlatform):
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)
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m.d.comb += q[bit].eq(_q)
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def get_input(self, pin, port, attrs):
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def get_input(self, pin, port, attrs, invert):
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assert not invert
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -150,7 +151,8 @@ class XilinxSpartan6Platform(TemplatedPlatform):
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m.d.comb += pin.i.eq(port)
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return m
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def get_output(self, pin, port, attrs):
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def get_output(self, pin, port, attrs, invert):
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assert not invert
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -160,7 +162,8 @@ class XilinxSpartan6Platform(TemplatedPlatform):
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m.d.comb += port.eq(pin.o)
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return m
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def get_tristate(self, pin, port, attrs):
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def get_tristate(self, pin, port, attrs, invert):
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assert not invert
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -177,7 +180,8 @@ class XilinxSpartan6Platform(TemplatedPlatform):
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)
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return m
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def get_input_output(self, pin, port, attrs):
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def get_input_output(self, pin, port, attrs, invert):
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assert not invert
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -197,7 +201,8 @@ class XilinxSpartan6Platform(TemplatedPlatform):
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)
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return m
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def get_diff_input(self, pin, p_port, n_port, attrs):
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def get_diff_input(self, pin, p_port, n_port, attrs, invert):
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assert not invert
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -212,7 +217,8 @@ class XilinxSpartan6Platform(TemplatedPlatform):
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)
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return m
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def get_diff_output(self, pin, p_port, n_port, attrs):
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def get_diff_output(self, pin, p_port, n_port, attrs, invert):
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assert not invert
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -227,7 +233,8 @@ class XilinxSpartan6Platform(TemplatedPlatform):
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)
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return m
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def get_diff_tristate(self, pin, p_port, n_port, attrs):
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def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
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assert not invert
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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@ -245,7 +252,8 @@ class XilinxSpartan6Platform(TemplatedPlatform):
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)
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return m
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def get_diff_input_output(self, pin, p_port, n_port, attrs):
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def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
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assert not invert
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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