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hdl.mem: allow omitting memory simulation logic.

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Trying to transform very large arrays is slow.
This commit is contained in:
whitequark 2018-12-24 09:31:51 +00:00
parent d47c1f8a8a
commit f05bd2a137
1 changed files with 5 additions and 4 deletions
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9
nmigen/hdl/mem.py
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@ -6,7 +6,7 @@ from .ir import Instance
class Memory: class Memory:
def __init__(self, width, depth, init=None, name=None): def __init__(self, width, depth, init=None, name=None, simulate=True):
if not isinstance(width, int) or width < 0: if not isinstance(width, int) or width < 0:
raise TypeError("Memory width must be a non-negative integer, not '{!r}'" raise TypeError("Memory width must be a non-negative integer, not '{!r}'"
.format(width)) .format(width))
@ -29,8 +29,9 @@ class Memory:
# Array of signals for simulation. # Array of signals for simulation.
self._array = Array() self._array = Array()
for addr in range(self.depth): if simulate:
self._array.append(Signal(self.width, name="{}({})".format(name, addr))) for addr in range(self.depth):
self._array.append(Signal(self.width, name="{}({})".format(name, addr)))
self.init = init self.init = init
@ -45,7 +46,7 @@ class Memory:
raise ValueError("Memory initialization value count exceed memory depth ({} > {})" raise ValueError("Memory initialization value count exceed memory depth ({} > {})"
.format(len(self.init), self.depth)) .format(len(self.init), self.depth))
for addr in range(self.depth): for addr in range(len(self._array)):
if addr < len(self._init): if addr < len(self._init):
self._array[addr].reset = self._init[addr] self._array[addr].reset = self._init[addr]
else: else: