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build.dsl: allow assertions on subsignal widths.

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This is useful when building abstractions around resources where
the pin names are user-specified.

Fixes #129.
This commit is contained in:
whitequark 2019-07-08 10:32:41 +00:00
parent a7fbff94d8
commit f0c1c2cfeb
2 changed files with 18 additions and 4 deletions
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10
nmigen/test/test_build_dsl.py
View file

@ -59,6 +59,11 @@ class PinsTestCase(FHDLTestCase):
"connector pin pmod_0:1"):
p.map_names(mapping, p)
def test_wrong_assert_width(self):
with self.assertRaises(AssertionError,
msg="3 names are specified (0 1 2), but 4 names are expected"):
Pins("0 1 2", assert_width=4)
class DiffPairsTestCase(FHDLTestCase):
def test_basic(self):
@ -96,6 +101,11 @@ class DiffPairsTestCase(FHDLTestCase):
"and (pins io B0 B1) do not"):
dp = DiffPairs("A0", "B0 B1")
def test_wrong_assert_width(self):
with self.assertRaises(AssertionError,
msg="3 names are specified (0 1 2), but 4 names are expected"):
DiffPairs("0 1 2", "3 4 5", assert_width=4)
class AttrsTestCase(FHDLTestCase):
def test_basic(self):