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build.dsl: allow assertions on subsignal widths.

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This is useful when building abstractions around resources where
the pin names are user-specified.

Fixes #129.
This commit is contained in:
whitequark 2019-07-08 10:32:41 +00:00
parent a7fbff94d8
commit f0c1c2cfeb
2 changed files with 18 additions and 4 deletions
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12
nmigen/build/dsl.py
View file

@ -6,7 +6,7 @@ __all__ = ["Pins", "PinsN", "DiffPairs", "DiffPairsN",
class Pins: class Pins:
def __init__(self, names, *, dir="io", conn=None): def __init__(self, names, *, dir="io", conn=None, assert_width=None):
if not isinstance(names, str): if not isinstance(names, str):
raise TypeError("Names must be a whitespace-separated string, not {!r}" raise TypeError("Names must be a whitespace-separated string, not {!r}"
.format(names)) .format(names))
@ -23,6 +23,10 @@ class Pins:
raise TypeError("Direction must be one of \"i\", \"o\", \"oe\", or \"io\", not {!r}" raise TypeError("Direction must be one of \"i\", \"o\", \"oe\", or \"io\", not {!r}"
.format(dir)) .format(dir))
if assert_width is not None and len(names) != assert_width:
raise AssertionError("{} names are specified ({}), but {} names are expected"
.format(len(names), " ".join(names), assert_width))
self.names = names self.names = names
self.dir = dir self.dir = dir
self.invert = False self.invert = False
@ -56,9 +60,9 @@ def PinsN(*args, **kwargs):
class DiffPairs: class DiffPairs:
def __init__(self, p, n, *, dir="io", conn=None): def __init__(self, p, n, *, dir="io", conn=None, assert_width=None):
self.p = Pins(p, dir=dir, conn=conn) self.p = Pins(p, dir=dir, conn=conn, assert_width=assert_width)
self.n = Pins(n, dir=dir, conn=conn) self.n = Pins(n, dir=dir, conn=conn, assert_width=assert_width)
if len(self.p.names) != len(self.n.names): if len(self.p.names) != len(self.n.names):
raise TypeError("Positive and negative pins must have the same width, but {!r} " raise TypeError("Positive and negative pins must have the same width, but {!r} "

10
nmigen/test/test_build_dsl.py
View file

@ -59,6 +59,11 @@ class PinsTestCase(FHDLTestCase):
"connector pin pmod_0:1"): "connector pin pmod_0:1"):
p.map_names(mapping, p) p.map_names(mapping, p)
def test_wrong_assert_width(self):
with self.assertRaises(AssertionError,
msg="3 names are specified (0 1 2), but 4 names are expected"):
Pins("0 1 2", assert_width=4)
class DiffPairsTestCase(FHDLTestCase): class DiffPairsTestCase(FHDLTestCase):
def test_basic(self): def test_basic(self):
@ -96,6 +101,11 @@ class DiffPairsTestCase(FHDLTestCase):
"and (pins io B0 B1) do not"): "and (pins io B0 B1) do not"):
dp = DiffPairs("A0", "B0 B1") dp = DiffPairs("A0", "B0 B1")
def test_wrong_assert_width(self):
with self.assertRaises(AssertionError,
msg="3 names are specified (0 1 2), but 4 names are expected"):
DiffPairs("0 1 2", "3 4 5", assert_width=4)
class AttrsTestCase(FHDLTestCase): class AttrsTestCase(FHDLTestCase):
def test_basic(self): def test_basic(self):