fhdl.ast: bits_sign→shape.
This commit is contained in:
whitequark
parent
dc486ad8b9
commit
f0f4c0ce61
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@ -285,8 +285,8 @@ class _ValueTransformer(xfrm.ValueTransformer):
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def on_Operator_unary(self, node):
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arg, = node.operands
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arg_bits, arg_sign = arg.bits_sign()
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res_bits, res_sign = node.bits_sign()
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arg_bits, arg_sign = arg.shape()
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res_bits, res_sign = node.shape()
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res = self.rtlil.wire(width=res_bits)
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self.rtlil.cell(self.operator_map[(1, node.op)], ports={
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"\\A": self(arg),
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@ -298,11 +298,11 @@ class _ValueTransformer(xfrm.ValueTransformer):
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})
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return res
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def match_bits_sign(self, node, new_bits, new_sign):
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def match_shape(self, node, new_bits, new_sign):
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if isinstance(node, ast.Const):
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return self(ast.Const(node.value, (new_bits, new_sign)))
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node_bits, node_sign = node.bits_sign()
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node_bits, node_sign = node.shape()
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if new_bits > node_bits:
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res = self.rtlil.wire(width=new_bits)
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self.rtlil.cell("$pos", ports={
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@ -319,17 +319,17 @@ class _ValueTransformer(xfrm.ValueTransformer):
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def on_Operator_binary(self, node):
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lhs, rhs = node.operands
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lhs_bits, lhs_sign = lhs.bits_sign()
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rhs_bits, rhs_sign = rhs.bits_sign()
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lhs_bits, lhs_sign = lhs.shape()
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rhs_bits, rhs_sign = rhs.shape()
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if lhs_sign == rhs_sign:
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lhs_wire = self(lhs)
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rhs_wire = self(rhs)
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else:
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lhs_sign = rhs_sign = True
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lhs_bits = rhs_bits = max(lhs_bits, rhs_bits)
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lhs_wire = self.match_bits_sign(lhs, lhs_bits, lhs_sign)
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rhs_wire = self.match_bits_sign(rhs, rhs_bits, rhs_sign)
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res_bits, res_sign = node.bits_sign()
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lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
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rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
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res_bits, res_sign = node.shape()
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res = self.rtlil.wire(width=res_bits)
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self.rtlil.cell(self.operator_map[(2, node.op)], ports={
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"\\A": lhs_wire,
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@ -346,9 +346,9 @@ class _ValueTransformer(xfrm.ValueTransformer):
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def on_Operator_mux(self, node):
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sel, lhs, rhs = node.operands
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lhs_bits, lhs_sign = lhs.bits_sign()
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rhs_bits, rhs_sign = rhs.bits_sign()
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res_bits, res_sign = node.bits_sign()
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lhs_bits, lhs_sign = lhs.shape()
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rhs_bits, rhs_sign = rhs.shape()
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res_bits, res_sign = node.shape()
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res = self.rtlil.wire(width=res_bits)
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self.rtlil.cell("$mux", ports={
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"\\A": self(lhs),
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@ -418,12 +418,12 @@ def convert_fragment(builder, fragment, name, clock_domains):
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def _convert_stmts(case, stmts):
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for stmt in stmts:
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if isinstance(stmt, ast.Assign):
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lhs_bits, lhs_sign = stmt.lhs.bits_sign()
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rhs_bits, rhs_sign = stmt.rhs.bits_sign()
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lhs_bits, lhs_sign = stmt.lhs.shape()
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rhs_bits, rhs_sign = stmt.rhs.shape()
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if lhs_bits == rhs_bits:
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rhs_sigspec = xformer(stmt.rhs)
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else:
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rhs_sigspec = xformer.match_bits_sign(
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rhs_sigspec = xformer.match_shape(
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stmt.rhs, lhs_bits, rhs_sign)
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with xformer.lhs():
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lhs_sigspec = xformer(stmt.lhs)
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@ -16,6 +16,6 @@ def bits_for(n, require_sign_bit=False):
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return tools.bits_for(n, require_sign_bit)
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@deprecated("instead of `value_bits_sign(v)`, use `v.bits_sign()`")
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@deprecated("instead of `value_bits_sign(v)`, use `v.shape()`")
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def value_bits_sign(v):
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return ast.Value.wrap(v).bits_sign()
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return ast.Value.wrap(v).shape()
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@ -98,7 +98,7 @@ class Value:
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return Operator(">=", [self, other])
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def __len__(self):
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return self.bits_sign()[0]
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return self.shape()[0]
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def __getitem__(self, key):
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n = len(self)
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@ -160,7 +160,7 @@ class Value:
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"""
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return Assign(self, value)
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def bits_sign(self):
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def shape(self):
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"""Bit length and signedness of a value.
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Returns
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@ -171,9 +171,9 @@ class Value:
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Examples
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--------
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>>> Value.bits_sign(Signal(8))
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>>> Value.shape(Signal(8))
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8, False
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>>> Value.bits_sign(C(0xaa))
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>>> Value.shape(C(0xaa))
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8, False
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"""
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raise NotImplementedError # :nocov:
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@ -194,10 +194,10 @@ class Const(Value):
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Parameters
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----------
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value : int
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bits_sign : int or tuple or None
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shape : int or tuple or None
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Either an integer `bits` or a tuple `(bits, signed)`
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specifying the number of bits in this `Const` and whether it is
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signed (can represent negative values). `bits_sign` defaults
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signed (can represent negative values). `shape` defaults
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to the minimum width and signedness of `value`.
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Attributes
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@ -205,17 +205,17 @@ class Const(Value):
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nbits : int
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signed : bool
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"""
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def __init__(self, value, bits_sign=None):
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def __init__(self, value, shape=None):
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self.value = int(value)
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if bits_sign is None:
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bits_sign = self.value.bit_length(), self.value < 0
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if isinstance(bits_sign, int):
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bits_sign = bits_sign, self.value < 0
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self.nbits, self.signed = bits_sign
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if shape is None:
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shape = self.value.bit_length(), self.value < 0
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if isinstance(shape, int):
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shape = shape, self.value < 0
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self.nbits, self.signed = shape
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if not isinstance(self.nbits, int) or self.nbits < 0:
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raise TypeError("Width must be a positive integer")
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def bits_sign(self):
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def shape(self):
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return self.nbits, self.signed
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def _rhs_signals(self):
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@ -235,7 +235,7 @@ class Operator(Value):
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self.operands = [Value.wrap(o) for o in operands]
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@staticmethod
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def _bitwise_binary_bits_sign(a, b):
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def _bitwise_binary_shape(a, b):
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if not a[1] and not b[1]:
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# both operands unsigned
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return max(a[0], b[0]), False
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@ -249,15 +249,15 @@ class Operator(Value):
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# first signed, second operand unsigned (add sign bit)
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return max(a[0], b[0] + 1), True
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def bits_sign(self):
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obs = list(map(lambda x: x.bits_sign(), self.operands))
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def shape(self):
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obs = list(map(lambda x: x.shape(), self.operands))
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if self.op == "+" or self.op == "-":
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if len(obs) == 1:
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if self.op == "-" and not obs[0][1]:
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return obs[0][0] + 1, True
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else:
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return obs[0]
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n, s = self._bitwise_binary_bits_sign(*obs)
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n, s = self._bitwise_binary_shape(*obs)
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return n + 1, s
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elif self.op == "*":
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if not obs[0][1] and not obs[1][1]:
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@ -282,14 +282,14 @@ class Operator(Value):
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extra = 0
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return obs[0][0] + extra, obs[0][1]
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elif self.op == "&" or self.op == "^" or self.op == "|":
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return self._bitwise_binary_bits_sign(*obs)
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return self._bitwise_binary_shape(*obs)
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elif (self.op == "<" or self.op == "<=" or self.op == "==" or self.op == "!=" or
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self.op == ">" or self.op == ">=" or self.op == "b"):
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return 1, False
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elif self.op == "~":
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return obs[0]
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elif self.op == "m":
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return self._bitwise_binary_bits_sign(obs[1], obs[2])
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return self._bitwise_binary_shape(obs[1], obs[2])
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else:
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raise TypeError # :nocov:
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@ -341,7 +341,7 @@ class Slice(Value):
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self.start = start
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self.end = end
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def bits_sign(self):
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def shape(self):
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return self.end - self.start, False
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def _lhs_signals(self):
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@ -364,7 +364,7 @@ class Part(Value):
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self.offset = Value.wrap(offset)
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self.width = width
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def bits_sign(self):
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def shape(self):
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return self.width, False
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def _lhs_signals(self):
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@ -405,7 +405,7 @@ class Cat(Value):
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super().__init__()
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self.operands = [Value.wrap(v) for v in flatten(args)]
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def bits_sign(self):
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def shape(self):
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return sum(len(op) for op in self.operands), False
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def _lhs_signals(self):
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@ -446,7 +446,7 @@ class Repl(Value):
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self.value = Value.wrap(value)
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self.count = count
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def bits_sign(self):
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def shape(self):
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return len(self.value) * self.count, False
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def _rhs_signals(self):
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@ -461,10 +461,10 @@ class Signal(Value, DUID):
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Parameters
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----------
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bits_sign : int or tuple or None
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shape : int or tuple or None
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Either an integer ``bits`` or a tuple ``(bits, signed)`` specifying the number of bits
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in this ``Signal`` and whether it is signed (can represent negative values).
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``bits_sign`` defaults to 1-bit and non-signed.
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``shape`` defaults to 1-bit and non-signed.
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name : str
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Name hint for this signal. If ``None`` (default) the name is inferred from the variable
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name this ``Signal`` is assigned to. Name collisions are automatically resolved by
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@ -482,9 +482,9 @@ class Signal(Value, DUID):
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Defaults to ``False``.
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min : int or None
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max : int or None
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If `bits_sign` is `None`, the signal bit width and signedness are
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determined by the integer range given by `min` (inclusive,
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defaults to 0) and `max` (exclusive, defaults to 2).
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If ``shape`` is ``None``, the signal bit width and signedness are
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determined by the integer range given by ``min`` (inclusive,
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defaults to 0) and ``max`` (exclusive, defaults to 2).
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attrs : dict
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Dictionary of synthesis attributes.
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@ -498,7 +498,7 @@ class Signal(Value, DUID):
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attrs : dict
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"""
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def __init__(self, bits_sign=None, name=None, reset=0, reset_less=False, min=None, max=None,
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def __init__(self, shape=None, name=None, reset=0, reset_less=False, min=None, max=None,
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attrs=None):
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super().__init__()
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@ -509,7 +509,7 @@ class Signal(Value, DUID):
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name = "$signal"
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self.name = name
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if bits_sign is None:
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if shape is None:
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if min is None:
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min = 0
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if max is None:
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@ -524,10 +524,10 @@ class Signal(Value, DUID):
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else:
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if not (min is None and max is None):
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raise ValueError("Only one of bits/signedness or bounds may be specified")
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if isinstance(bits_sign, int):
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self.nbits, self.signed = bits_sign, False
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if isinstance(shape, int):
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self.nbits, self.signed = shape, False
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else:
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self.nbits, self.signed = bits_sign
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self.nbits, self.signed = shape
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if not isinstance(self.nbits, int) or self.nbits < 0:
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raise TypeError("Width must be a positive integer, not {!r}".format(self.nbits))
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@ -545,13 +545,13 @@ class Signal(Value, DUID):
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other : Value
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Object to base this Signal on.
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"""
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kw = dict(bits_sign=cls.wrap(other).bits_sign())
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kw = dict(shape=cls.wrap(other).shape())
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if isinstance(other, cls):
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kw.update(reset=other.reset, reset_less=other.reset_less, attrs=other.attrs)
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kw.update(kwargs)
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return cls(**kw)
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def bits_sign(self):
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def shape(self):
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return self.nbits, self.signed
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def _lhs_signals(self):
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@ -10,8 +10,8 @@ class MultiReg:
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self.o = o
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self.odomain = odomain
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self._regs = [Signal(self.i.bits_sign(), name="cdc{}".format(i),
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reset=reset, reset_less=True, attrs={"no_retiming": True})
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self._regs = [Signal(self.i.shape(), name="cdc{}".format(i), reset=reset, reset_less=True,
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attrs={"no_retiming": True})
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for i in range(n)]
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def get_fragment(self, platform):
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@ -59,14 +59,14 @@ class ValueTestCase(unittest.TestCase):
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class ConstTestCase(unittest.TestCase):
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def test_bits_sign(self):
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self.assertEqual(Const(0).bits_sign(), (0, False))
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self.assertEqual(Const(1).bits_sign(), (1, False))
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self.assertEqual(Const(10).bits_sign(), (4, False))
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self.assertEqual(Const(-10).bits_sign(), (4, True))
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def test_shape(self):
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self.assertEqual(Const(0).shape(), (0, False))
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self.assertEqual(Const(1).shape(), (1, False))
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self.assertEqual(Const(10).shape(), (4, False))
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self.assertEqual(Const(-10).shape(), (4, True))
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self.assertEqual(Const(1, 4).bits_sign(), (4, False))
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self.assertEqual(Const(1, (4, True)).bits_sign(), (4, True))
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self.assertEqual(Const(1, 4).shape(), (4, False))
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self.assertEqual(Const(1, (4, True)).shape(), (4, True))
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with self.assertRaises(TypeError):
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Const(1, -1)
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@ -87,138 +87,138 @@ class OperatorTestCase(unittest.TestCase):
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def test_invert(self):
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v = ~Const(0, 4)
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self.assertEqual(repr(v), "(~ (const 4'd0))")
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self.assertEqual(v.bits_sign(), (4, False))
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self.assertEqual(v.shape(), (4, False))
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def test_neg(self):
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v1 = -Const(0, (4, False))
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self.assertEqual(repr(v1), "(- (const 4'd0))")
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self.assertEqual(v1.bits_sign(), (5, True))
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self.assertEqual(v1.shape(), (5, True))
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v2 = -Const(0, (4, True))
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self.assertEqual(repr(v2), "(- (const 4'sd0))")
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self.assertEqual(v2.bits_sign(), (4, True))
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self.assertEqual(v2.shape(), (4, True))
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def test_add(self):
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v1 = Const(0, (4, False)) + Const(0, (6, False))
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self.assertEqual(repr(v1), "(+ (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (7, False))
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self.assertEqual(v1.shape(), (7, False))
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v2 = Const(0, (4, True)) + Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (7, True))
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self.assertEqual(v2.shape(), (7, True))
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v3 = Const(0, (4, True)) + Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (6, True))
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self.assertEqual(v3.shape(), (6, True))
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v4 = Const(0, (4, False)) + Const(0, (4, True))
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self.assertEqual(v4.bits_sign(), (6, True))
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self.assertEqual(v4.shape(), (6, True))
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v5 = 10 + Const(0, 4)
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self.assertEqual(v5.bits_sign(), (5, False))
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self.assertEqual(v5.shape(), (5, False))
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def test_sub(self):
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v1 = Const(0, (4, False)) - Const(0, (6, False))
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self.assertEqual(repr(v1), "(- (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (7, False))
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self.assertEqual(v1.shape(), (7, False))
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v2 = Const(0, (4, True)) - Const(0, (6, True))
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self.assertEqual(v2.bits_sign(), (7, True))
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self.assertEqual(v2.shape(), (7, True))
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v3 = Const(0, (4, True)) - Const(0, (4, False))
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self.assertEqual(v3.bits_sign(), (6, True))
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self.assertEqual(v3.shape(), (6, True))
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v4 = Const(0, (4, False)) - Const(0, (4, True))
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self.assertEqual(v4.bits_sign(), (6, True))
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self.assertEqual(v4.shape(), (6, True))
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v5 = 10 - Const(0, 4)
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self.assertEqual(v5.bits_sign(), (5, False))
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self.assertEqual(v5.shape(), (5, False))
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def test_mul(self):
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v1 = Const(0, (4, False)) * Const(0, (6, False))
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self.assertEqual(repr(v1), "(* (const 4'd0) (const 6'd0))")
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self.assertEqual(v1.bits_sign(), (10, False))
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self.assertEqual(v1.shape(), (10, False))
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v2 = Const(0, (4, True)) * Const(0, (6, True))
|
||||
self.assertEqual(v2.bits_sign(), (9, True))
|
||||
self.assertEqual(v2.shape(), (9, True))
|
||||
v3 = Const(0, (4, True)) * Const(0, (4, False))
|
||||
self.assertEqual(v3.bits_sign(), (8, True))
|
||||
self.assertEqual(v3.shape(), (8, True))
|
||||
v5 = 10 * Const(0, 4)
|
||||
self.assertEqual(v5.bits_sign(), (8, False))
|
||||
self.assertEqual(v5.shape(), (8, False))
|
||||
|
||||
def test_and(self):
|
||||
v1 = Const(0, (4, False)) & Const(0, (6, False))
|
||||
self.assertEqual(repr(v1), "(& (const 4'd0) (const 6'd0))")
|
||||
self.assertEqual(v1.bits_sign(), (6, False))
|
||||
self.assertEqual(v1.shape(), (6, False))
|
||||
v2 = Const(0, (4, True)) & Const(0, (6, True))
|
||||
self.assertEqual(v2.bits_sign(), (6, True))
|
||||
self.assertEqual(v2.shape(), (6, True))
|
||||
v3 = Const(0, (4, True)) & Const(0, (4, False))
|
||||
self.assertEqual(v3.bits_sign(), (5, True))
|
||||
self.assertEqual(v3.shape(), (5, True))
|
||||
v4 = Const(0, (4, False)) & Const(0, (4, True))
|
||||
self.assertEqual(v4.bits_sign(), (5, True))
|
||||
self.assertEqual(v4.shape(), (5, True))
|
||||
v5 = 10 & Const(0, 4)
|
||||
self.assertEqual(v5.bits_sign(), (4, False))
|
||||
self.assertEqual(v5.shape(), (4, False))
|
||||
|
||||
def test_or(self):
|
||||
v1 = Const(0, (4, False)) | Const(0, (6, False))
|
||||
self.assertEqual(repr(v1), "(| (const 4'd0) (const 6'd0))")
|
||||
self.assertEqual(v1.bits_sign(), (6, False))
|
||||
self.assertEqual(v1.shape(), (6, False))
|
||||
v2 = Const(0, (4, True)) | Const(0, (6, True))
|
||||
self.assertEqual(v2.bits_sign(), (6, True))
|
||||
self.assertEqual(v2.shape(), (6, True))
|
||||
v3 = Const(0, (4, True)) | Const(0, (4, False))
|
||||
self.assertEqual(v3.bits_sign(), (5, True))
|
||||
self.assertEqual(v3.shape(), (5, True))
|
||||
v4 = Const(0, (4, False)) | Const(0, (4, True))
|
||||
self.assertEqual(v4.bits_sign(), (5, True))
|
||||
self.assertEqual(v4.shape(), (5, True))
|
||||
v5 = 10 | Const(0, 4)
|
||||
self.assertEqual(v5.bits_sign(), (4, False))
|
||||
self.assertEqual(v5.shape(), (4, False))
|
||||
|
||||
def test_xor(self):
|
||||
v1 = Const(0, (4, False)) ^ Const(0, (6, False))
|
||||
self.assertEqual(repr(v1), "(^ (const 4'd0) (const 6'd0))")
|
||||
self.assertEqual(v1.bits_sign(), (6, False))
|
||||
self.assertEqual(v1.shape(), (6, False))
|
||||
v2 = Const(0, (4, True)) ^ Const(0, (6, True))
|
||||
self.assertEqual(v2.bits_sign(), (6, True))
|
||||
self.assertEqual(v2.shape(), (6, True))
|
||||
v3 = Const(0, (4, True)) ^ Const(0, (4, False))
|
||||
self.assertEqual(v3.bits_sign(), (5, True))
|
||||
self.assertEqual(v3.shape(), (5, True))
|
||||
v4 = Const(0, (4, False)) ^ Const(0, (4, True))
|
||||
self.assertEqual(v4.bits_sign(), (5, True))
|
||||
self.assertEqual(v4.shape(), (5, True))
|
||||
v5 = 10 ^ Const(0, 4)
|
||||
self.assertEqual(v5.bits_sign(), (4, False))
|
||||
self.assertEqual(v5.shape(), (4, False))
|
||||
|
||||
def test_lt(self):
|
||||
v = Const(0, 4) < Const(0, 6)
|
||||
self.assertEqual(repr(v), "(< (const 4'd0) (const 6'd0))")
|
||||
self.assertEqual(v.bits_sign(), (1, False))
|
||||
self.assertEqual(v.shape(), (1, False))
|
||||
|
||||
def test_le(self):
|
||||
v = Const(0, 4) <= Const(0, 6)
|
||||
self.assertEqual(repr(v), "(<= (const 4'd0) (const 6'd0))")
|
||||
self.assertEqual(v.bits_sign(), (1, False))
|
||||
self.assertEqual(v.shape(), (1, False))
|
||||
|
||||
def test_gt(self):
|
||||
v = Const(0, 4) > Const(0, 6)
|
||||
self.assertEqual(repr(v), "(> (const 4'd0) (const 6'd0))")
|
||||
self.assertEqual(v.bits_sign(), (1, False))
|
||||
self.assertEqual(v.shape(), (1, False))
|
||||
|
||||
def test_ge(self):
|
||||
v = Const(0, 4) >= Const(0, 6)
|
||||
self.assertEqual(repr(v), "(>= (const 4'd0) (const 6'd0))")
|
||||
self.assertEqual(v.bits_sign(), (1, False))
|
||||
self.assertEqual(v.shape(), (1, False))
|
||||
|
||||
def test_eq(self):
|
||||
v = Const(0, 4) == Const(0, 6)
|
||||
self.assertEqual(repr(v), "(== (const 4'd0) (const 6'd0))")
|
||||
self.assertEqual(v.bits_sign(), (1, False))
|
||||
self.assertEqual(v.shape(), (1, False))
|
||||
|
||||
def test_ne(self):
|
||||
v = Const(0, 4) != Const(0, 6)
|
||||
self.assertEqual(repr(v), "(!= (const 4'd0) (const 6'd0))")
|
||||
self.assertEqual(v.bits_sign(), (1, False))
|
||||
self.assertEqual(v.shape(), (1, False))
|
||||
|
||||
def test_mux(self):
|
||||
s = Const(0)
|
||||
v1 = Mux(s, Const(0, (4, False)), Const(0, (6, False)))
|
||||
self.assertEqual(repr(v1), "(m (const 0'd0) (const 4'd0) (const 6'd0))")
|
||||
self.assertEqual(v1.bits_sign(), (6, False))
|
||||
self.assertEqual(v1.shape(), (6, False))
|
||||
v2 = Mux(s, Const(0, (4, True)), Const(0, (6, True)))
|
||||
self.assertEqual(v2.bits_sign(), (6, True))
|
||||
self.assertEqual(v2.shape(), (6, True))
|
||||
v3 = Mux(s, Const(0, (4, True)), Const(0, (4, False)))
|
||||
self.assertEqual(v3.bits_sign(), (5, True))
|
||||
self.assertEqual(v3.shape(), (5, True))
|
||||
v4 = Mux(s, Const(0, (4, False)), Const(0, (4, True)))
|
||||
self.assertEqual(v4.bits_sign(), (5, True))
|
||||
self.assertEqual(v4.shape(), (5, True))
|
||||
|
||||
def test_bool(self):
|
||||
v = Const(0).bool()
|
||||
self.assertEqual(repr(v), "(b (const 0'd0))")
|
||||
self.assertEqual(v.bits_sign(), (1, False))
|
||||
self.assertEqual(v.shape(), (1, False))
|
||||
|
||||
def test_hash(self):
|
||||
with self.assertRaises(TypeError):
|
||||
|
|
@ -226,11 +226,11 @@ class OperatorTestCase(unittest.TestCase):
|
|||
|
||||
|
||||
class SliceTestCase(unittest.TestCase):
|
||||
def test_bits_sign(self):
|
||||
def test_shape(self):
|
||||
s1 = Const(10)[2]
|
||||
self.assertEqual(s1.bits_sign(), (1, False))
|
||||
self.assertEqual(s1.shape(), (1, False))
|
||||
s2 = Const(-10)[0:2]
|
||||
self.assertEqual(s2.bits_sign(), (2, False))
|
||||
self.assertEqual(s2.shape(), (2, False))
|
||||
|
||||
def test_repr(self):
|
||||
s1 = Const(10)[2]
|
||||
|
|
@ -238,13 +238,13 @@ class SliceTestCase(unittest.TestCase):
|
|||
|
||||
|
||||
class CatTestCase(unittest.TestCase):
|
||||
def test_bits_sign(self):
|
||||
def test_shape(self):
|
||||
c1 = Cat(Const(10))
|
||||
self.assertEqual(c1.bits_sign(), (4, False))
|
||||
self.assertEqual(c1.shape(), (4, False))
|
||||
c2 = Cat(Const(10), Const(1))
|
||||
self.assertEqual(c2.bits_sign(), (5, False))
|
||||
self.assertEqual(c2.shape(), (5, False))
|
||||
c3 = Cat(Const(10), Const(1), Const(0))
|
||||
self.assertEqual(c3.bits_sign(), (5, False))
|
||||
self.assertEqual(c3.shape(), (5, False))
|
||||
|
||||
def test_repr(self):
|
||||
c1 = Cat(Const(10), Const(1))
|
||||
|
|
@ -252,9 +252,9 @@ class CatTestCase(unittest.TestCase):
|
|||
|
||||
|
||||
class ReplTestCase(unittest.TestCase):
|
||||
def test_bits_sign(self):
|
||||
def test_shape(self):
|
||||
r1 = Repl(Const(10), 3)
|
||||
self.assertEqual(r1.bits_sign(), (12, False))
|
||||
self.assertEqual(r1.shape(), (12, False))
|
||||
|
||||
def test_count_wrong(self):
|
||||
with self.assertRaises(TypeError):
|
||||
|
|
@ -268,23 +268,23 @@ class ReplTestCase(unittest.TestCase):
|
|||
|
||||
|
||||
class SignalTestCase(unittest.TestCase):
|
||||
def test_bits_sign(self):
|
||||
def test_shape(self):
|
||||
s1 = Signal()
|
||||
self.assertEqual(s1.bits_sign(), (1, False))
|
||||
self.assertEqual(s1.shape(), (1, False))
|
||||
s2 = Signal(2)
|
||||
self.assertEqual(s2.bits_sign(), (2, False))
|
||||
self.assertEqual(s2.shape(), (2, False))
|
||||
s3 = Signal((2, False))
|
||||
self.assertEqual(s3.bits_sign(), (2, False))
|
||||
self.assertEqual(s3.shape(), (2, False))
|
||||
s4 = Signal((2, True))
|
||||
self.assertEqual(s4.bits_sign(), (2, True))
|
||||
self.assertEqual(s4.shape(), (2, True))
|
||||
s5 = Signal(max=16)
|
||||
self.assertEqual(s5.bits_sign(), (4, False))
|
||||
self.assertEqual(s5.shape(), (4, False))
|
||||
s6 = Signal(min=4, max=16)
|
||||
self.assertEqual(s6.bits_sign(), (4, False))
|
||||
self.assertEqual(s6.shape(), (4, False))
|
||||
s7 = Signal(min=-4, max=16)
|
||||
self.assertEqual(s7.bits_sign(), (5, True))
|
||||
self.assertEqual(s7.shape(), (5, True))
|
||||
s8 = Signal(min=-20, max=16)
|
||||
self.assertEqual(s8.bits_sign(), (6, True))
|
||||
self.assertEqual(s8.shape(), (6, True))
|
||||
|
||||
with self.assertRaises(ValueError):
|
||||
Signal(min=10, max=4)
|
||||
|
|
@ -316,16 +316,16 @@ class SignalTestCase(unittest.TestCase):
|
|||
|
||||
def test_like(self):
|
||||
s1 = Signal.like(Signal(4))
|
||||
self.assertEqual(s1.bits_sign(), (4, False))
|
||||
self.assertEqual(s1.shape(), (4, False))
|
||||
s2 = Signal.like(Signal(min=-15))
|
||||
self.assertEqual(s2.bits_sign(), (5, True))
|
||||
self.assertEqual(s2.shape(), (5, True))
|
||||
s3 = Signal.like(Signal(4, reset=0b111, reset_less=True))
|
||||
self.assertEqual(s3.reset, 0b111)
|
||||
self.assertEqual(s3.reset_less, True)
|
||||
s4 = Signal.like(Signal(attrs={"no_retiming": True}))
|
||||
self.assertEqual(s4.attrs, {"no_retiming": True})
|
||||
s5 = Signal.like(10)
|
||||
self.assertEqual(s5.bits_sign(), (4, False))
|
||||
self.assertEqual(s5.shape(), (4, False))
|
||||
|
||||
|
||||
class ClockSignalTestCase(unittest.TestCase):
|
||||
|
|
|
|||
Loading…
Reference in a new issue