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back.rtlil: update for Yosys master.

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This commit is contained in:
whitequark 2018-12-17 15:50:43 +00:00
parent 850674637a
commit f1e390cbc9
1 changed files with 1 additions and 3 deletions
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4
nmigen/back/rtlil.py
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@ -451,9 +451,7 @@ class _RHSValueCompiler(_ValueCompiler):
raise TypeError # :nocov: raise TypeError # :nocov:
def _prepare_value_for_Slice(self, value): def _prepare_value_for_Slice(self, value):
# Uncomment after the following is merged: https://github.com/YosysHQ/yosys/pull/741 if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)):
# if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)):
if isinstance(value, ast.Signal):
sigspec = self(value) sigspec = self(value)
else: else:
sigspec = self.s.rtlil.wire(len(value)) sigspec = self.s.rtlil.wire(len(value))