back.rtlil: update for Yosys master.

2018-12-17 15:50:43 +00:00 · 2018-12-17 15:50:43 +00:00 · f1e390cbc9
parent 850674637a
commit f1e390cbc9
1 changed files with 1 additions and 3 deletions
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@ -451,9 +451,7 @@ class _RHSValueCompiler(_ValueCompiler):
            raise TypeError # :nocov:

    def _prepare_value_for_Slice(self, value):
-        # Uncomment after the following is merged: https://github.com/YosysHQ/yosys/pull/741
-        # if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)):
-        if isinstance(value, ast.Signal):
+        if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)):
            sigspec = self(value)
        else:
            sigspec = self.s.rtlil.wire(len(value))