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vendor.xilinx_*: Set IOB attribute on cels instead of nets.

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Jean-François Nguyen 2019-11-18 15:58:39 +01:00 committed by whitequark
parent 7c322e562a
commit f207f3f620
3 changed files with 6 additions and 18 deletions
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9
nmigen/vendor/xilinx_7series.py vendored
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@ -175,19 +175,14 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
def get_dff(clk, d, q):
# SDR I/O is performed by packing a flip-flop into the pad IOB.
for bit in range(len(q)):
_q = Signal()
_q.attrs["IOB"] = "TRUE"
# Vivado 2019.1 seems to make this flip-flop ineligible for IOB packing unless
# we prevent it from being optimized.
_q.attrs["DONT_TOUCH"] = "TRUE"
m.submodules += Instance("FDCE",
a_IOB="TRUE",
i_C=clk,
i_CE=Const(1),
i_CLR=Const(0),
i_D=d[bit],
o_Q=_q
o_Q=q[bit]
)
m.d.comb += q[bit].eq(_q)
def get_iddr(clk, d, q1, q2):
for bit in range(len(q1)):

6
nmigen/vendor/xilinx_spartan_3_6.py vendored
View file

@ -212,16 +212,14 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
def get_dff(clk, d, q):
# SDR I/O is performed by packing a flip-flop into the pad IOB.
for bit in range(len(q)):
_q = Signal()
_q.attrs["IOB"] = "TRUE"
m.submodules += Instance("FDCE",
a_IOB="TRUE",
i_C=clk,
i_CE=Const(1),
i_CLR=Const(0),
i_D=d[bit],
o_Q=_q,
o_Q=q[bit]
)
m.d.comb += q[bit].eq(_q)
def get_iddr(clk, d, q0, q1):
for bit in range(len(q0)):

9
nmigen/vendor/xilinx_ultrascale.py vendored
View file

@ -175,19 +175,14 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
def get_dff(clk, d, q):
# SDR I/O is performed by packing a flip-flop into the pad IOB.
for bit in range(len(q)):
_q = Signal()
_q.attrs["IOB"] = "TRUE"
# Vivado 2019.1 seems to make this flip-flop ineligible for IOB packing unless
# we prevent it from being optimized.
_q.attrs["DONT_TOUCH"] = "TRUE"
m.submodules += Instance("FDCE",
a_IOB="TRUE",
i_C=clk,
i_CE=Const(1),
i_CLR=Const(0),
i_D=d[bit],
o_Q=_q
o_Q=q[bit]
)
m.d.comb += q[bit].eq(_q)
def get_iddr(clk, d, q1, q2):
for bit in range(len(q1)):