usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity

back.rtlil: allow record slices on LHS.

Browse source
This commit is contained in:
whitequark 2019-04-20 08:12:29 +00:00
parent 611c25f909
commit f22106e5ef
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
nmigen/back/rtlil.py
View file

@ -4,7 +4,7 @@ from collections import defaultdict, OrderedDict
from contextlib import contextmanager from contextlib import contextmanager
from ..tools import bits_for from ..tools import bits_for
from ..hdl import ast, ir, mem, xfrm from ..hdl import ast, rec, ir, mem, xfrm
__all__ = ["convert"] __all__ = ["convert"]
@ -563,7 +563,7 @@ class _LHSValueCompiler(_ValueCompiler):
return wire_next return wire_next
def _prepare_value_for_Slice(self, value): def _prepare_value_for_Slice(self, value):
assert isinstance(value, (ast.Signal, ast.Slice, ast.Cat)) assert isinstance(value, (ast.Signal, ast.Slice, ast.Cat, rec.Record))
return self(value) return self(value)
def on_Part(self, value): def on_Part(self, value):