vendor.xilinx_7series: implement.
This commit is contained in:
Jean-François Nguyen
whitequark
parent
b45c5119f5
commit
f26e612899
256
nmigen/vendor/xilinx_7series.py
vendored
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256
nmigen/vendor/xilinx_7series.py
vendored
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from abc import abstractproperty
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from ..hdl.ast import *
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from ..hdl.dsl import *
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from ..hdl.ir import *
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from ..build import *
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__all__ = ["Xilinx7SeriesPlatform"]
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class Xilinx7SeriesPlatform(TemplatedPlatform):
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"""
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Required tools:
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* ``vivado``
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Available overrides:
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* ``script_after_read``: inserts commands after ``read_xdc`` in Tcl script.
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* ``script_after_synth``: inserts commands after ``synth_design`` in Tcl script.
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* ``script_after_place``: inserts commands after ``place_design`` in Tcl script.
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* ``script_after_route``: inserts commands after ``route_design`` in Tcl script.
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* ``script_before_bitstream``: inserts commands before ``write_bitstream`` in Tcl script.
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* ``script_after_bitstream``: inserts commands after ``write_bitstream`` in Tcl script.
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* ``add_constraints``: inserts commands in XDC file.
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* ``vivado_opts``: adds extra options for Vivado.
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Build products:
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* ``{{name}}.log``: Vivado log.
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* ``{{name}}_timing_synth.rpt``: Vivado report.
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* ``{{name}}_utilization_hierarchical_synth.rpt``: Vivado report.
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* ``{{name}}_utilization_synth.rpt``: Vivado report.
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* ``{{name}}_utilization_hierarchical_place.rpt``: Vivado report.
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* ``{{name}}_utilization_place.rpt``: Vivado report.
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* ``{{name}}_io.rpt``: Vivado report.
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* ``{{name}}_control_sets.rpt``: Vivado report.
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* ``{{name}}_clock_utilization.rpt``: Vivado report.
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* ``{{name}}_route_status.rpt``: Vivado report.
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* ``{{name}}_drc.rpt``: Vivado report.
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* ``{{name}}_timing.rpt``: Vivado report.
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* ``{{name}}_power.rpt``: Vivado report.
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* ``{{name}}_route.dcp``: Vivado design checkpoint.
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* ``{{name}}.bit``: binary bitstream.
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"""
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device = abstractproperty()
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package = abstractproperty()
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speedgrade = abstractproperty()
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file_templates = {
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**TemplatedPlatform.build_script_templates,
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"{{name}}.v": r"""
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/* {{autogenerated}} */
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{{emit_design("verilog")}}
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""",
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"{{name}}.tcl": r"""
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# {{autogenerated}}
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create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speedgrade}}
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{% for file in platform.extra_files %}
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{% if file.endswith((".v", ".sv")) -%}
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add_files {{file}}
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{% endif %}
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{% endfor %}
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add_files {{name}}.v
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read_xdc {{name}}.xdc
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{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
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synth_design -top {{name}} -part {{platform.device}}
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{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
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report_timing_summary -file {{name}}_timing_synth.rpt
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report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt
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report_utilization -file {{name}}_utilization_synth.rpt
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opt_design
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place_design
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{{get_override("script_after_place")|default("# (script_after_place placeholder)")}}
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report_utilization -hierarchical -file {{name}}_utilization_hierarchical_place.rpt
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report_utilization -file {{name}}_utilization_place.rpt
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report_io -file {{name}}_io.rpt
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report_control_sets -verbose -file {{name}}_control_sets.rpt
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report_clock_utilization -file {{name}}_clock_utilization.rpt
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route_design
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{{get_override("script_after_route")|default("# (script_after_route placeholder)")}}
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phys_opt_design
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report_timing_summary -no_header -no_detailed_paths
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write_checkpoint -force {{name}}_route.dcp
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report_route_status -file {{name}}_route_status.rpt
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report_drc -file {{name}}_drc.rpt
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report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
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report_power -file {{name}}_power.rpt
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{{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}
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write_bitstream -force {{name}}.bit
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{{get_override("script_after_bitstream")|default("# (script_after_bitstream placeholder)")}}
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quit
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""",
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"{{name}}.xdc": r"""
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# {{autogenerated}}
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{% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
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set_property LOC {{pin_name}} [get_ports {{port_name}}]
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{% for attr_name, attr_value in attrs.items() -%}
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set_property {{attr_name}} {{attr_value}} [get_ports {{port_name}}]
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{% endfor %}
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{% endfor %}
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{% for signal, frequency in platform.iter_clock_constraints() -%}
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create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_ports {{signal.name}}]
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{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
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{% endfor %}
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"""
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}
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command_templates = [
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r"""
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{{get_tool("vivado")}}
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{{verbose("-verbose")}}
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{{get_override("vivado_opts")|join(" ")}}
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-mode batch
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-log {{name}}.log
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-source {{name}}.tcl
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"""
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]
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def _get_dff(self, m, clk, d, q):
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# SDR I/O is performed by packing a flip-flop into the pad IOB.
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for bit in range(len(q)):
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_q = Signal()
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_q.attrs["IOB"] = "TRUE"
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m.submodules += Instance("FDCE",
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i_C=clk,
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i_CE=Const(1),
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i_CLR=Const(0),
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i_D=d[bit],
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o_Q=_q,
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)
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m.d.comb += q[bit].eq(_q)
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def get_input(self, pin, port, attrs):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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self._get_dff(m, pin.i_clk, port, pin.i)
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else:
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m.d.comb += pin.i.eq(port)
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return m
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def get_output(self, pin, port, attrs):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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self._get_dff(m, pin.o_clk, pin.o, port)
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else:
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m.d.comb += port.eq(pin.o)
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return m
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def get_tristate(self, pin, port, attrs):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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oe_ff = Signal.like(pin.oe, name="{}_ff".format(pin.oe.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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self._get_dff(m, pin.o_clk, pin.oe, oe_ff)
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for bit in range(len(port)):
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m.submodules += Instance("OBUFT",
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i_T=~(oe_ff if pin.xdr == 1 else pin.oe),
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit],
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o_O=port[bit]
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)
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return m
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def get_input_output(self, pin, port, attrs):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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oe_ff = Signal.like(pin.oe, name="{}_ff".format(pin.oe.name))
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i_ff = Signal.like(pin.i, name="{}_ff".format(pin.i.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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self._get_dff(m, pin.o_clk, pin.oe, oe_ff)
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self._get_dff(m, pin.i_clk, i_ff, pin.i)
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for bit in range(len(port)):
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m.submodules += Instance("IOBUF",
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i_T=~(oe_ff if pin.xdr == 1 else pin.oe),
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit],
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o_O=i_ff[bit] if pin.xdr == 1 else pin.i[bit],
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io_IO=port[bit]
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)
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return m
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def get_diff_input(self, pin, p_port, n_port, attrs):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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i_ff = Signal.like(pin.i, name="{}_ff".format(pin.i.name))
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self._get_dff(m, pin.i_clk, i_ff, pin.i)
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for bit in range(len(p_port)):
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m.submodules += Instance("IBUFDS",
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i_I=p_port[bit],
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i_IB=n_port[bit],
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o_O=i_ff[bit] if pin.xdr == 1 else pin.i[bit]
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)
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return m
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def get_diff_output(self, pin, p_port, n_port, attrs):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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for bit in range(len(p_port)):
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m.submodules += Instance("OBUFDS",
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o_O=p_port[bit],
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o_OB=n_port[bit],
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit]
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)
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return m
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def get_diff_tristate(self, pin, p_port, n_port, attrs):
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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oe_ff = Signal.like(pin.oe, name="{}_ff".format(pin.oe.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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self._get_dff(m, pin.o_clk, pin.oe, oe_ff)
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for bit in range(len(p_port)):
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m.submodules += Instance("OBUFTDS",
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i_T=~(oe_ff if pin.xdr == 1 else pin.oe),
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit],
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o_O=p_port[bit],
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o_OB=n_port[bit]
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)
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return m
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def get_diff_input_output(self, pin, p_port, n_port, attrs):
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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m = Module()
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if pin.xdr == 1:
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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oe_ff = Signal.like(pin.oe, name="{}_ff".format(pin.oe.name))
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i_ff = Signal.like(pin.i, name="{}_ff".format(pin.i.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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self._get_dff(m, pin.o_clk, pin.oe, oe_ff)
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self._get_dff(m, pin.i_clk, i_ff, pin.i)
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for bit in range(len(p_port)):
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m.submodules += Instance("IOBUFDS",
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i_T=~(oe_ff if pin.xdr == 1 else pin.oe),
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit],
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o_O=i_ff[bit] if pin.xdr == 1 else pin.i[bit],
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io_IO=p_port[bit],
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io_IOB=n_port[bit]
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)
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return m
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