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back.rtlil: Generate RTLIL for Assert/Assume statements.

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William D. Jones 2019-01-01 01:31:54 -05:00 committed by whitequark
parent f77dc40256
commit f31055a4ef
1 changed files with 22 additions and 0 deletions
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22
nmigen/back/rtlil.py
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@ -565,6 +565,28 @@ class _StatementCompiler(xfrm.StatementVisitor):
stmt.rhs, lhs_bits, lhs_sign)
self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec)
def on_Assert(self, stmt):
self(stmt._check.eq(stmt.test))
self(stmt._en.eq(1))
en_wire = self.rhs_compiler(stmt._en)
check_wire = self.rhs_compiler(stmt._check)
self.state.rtlil.cell("$assert", ports={
"\\A": check_wire,
"\\EN": en_wire,
}, src=src(stmt.test.src_loc))
def on_Assume(self, stmt):
self(stmt._check.eq(stmt.test))
self(stmt._en.eq(1))
en_wire = self.rhs_compiler(stmt._en)
check_wire = self.rhs_compiler(stmt._check)
self.state.rtlil.cell("$assume", ports={
"\\A": check_wire,
"\\EN": en_wire,
}, src=src(stmt.test.src_loc))
def on_Switch(self, stmt):
self._check_rhs(stmt.test)