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vendor.xilinx_7series: apply false path / max delay constraints.

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This commit is contained in:
Darrell Harmon 2019-09-23 18:47:54 -06:00 • committed by whitequark
parent da53048ad4
commit f3a8880cb8
5 changed files with 70 additions and 7 deletions
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33
nmigen/lib/cdc.py
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@ -29,15 +29,18 @@ class FFSynchronizer(Elaboratable):
Signal connected to synchroniser output.
o_domain : str
Name of output clock domain.
stages : int
Number of synchronization stages between input and output. The lowest safe number is 2,
with higher numbers reducing MTBF further, at the cost of increased latency.
reset : int
Reset value of the flip-flops. On FPGAs, even if ``reset_less`` is True,
the :class:`FFSynchronizer` is still set to this value during initialization.
reset_less : bool
If True (the default), this :class:`FFSynchronizer` is unaffected by ``o_domain`` reset.
See "Note on Reset" below.
If ``True`` (the default), this :class:`FFSynchronizer` is unaffected by ``o_domain``
reset. See "Note on Reset" below.
stages : int
Number of synchronization stages between input and output. The lowest safe number is 2,
with higher numbers reducing MTBF further, at the cost of increased latency.
max_input_delay : None or float
Maximum delay from the input signal's clock to the first synchronization stage.
If specified and the platform does not support it, elaboration will fail.
Platform override
-----------------
@ -61,7 +64,8 @@ class FFSynchronizer(Elaboratable):
:class:`FFSynchronizer` is reset by the ``o_domain`` reset only.
"""
def __init__(self, i, o, *, o_domain="sync", reset=0, reset_less=True, stages=2):
def __init__(self, i, o, *, o_domain="sync", reset=0, reset_less=True, stages=2,
max_input_delay=None):
_check_stages(stages)
self.i = i
@ -72,10 +76,16 @@ class FFSynchronizer(Elaboratable):
self._o_domain = o_domain
self._stages = stages
self._max_input_delay = max_input_delay
def elaborate(self, platform):
if hasattr(platform, "get_ff_sync"):
return platform.get_ff_sync(self)
if self._max_input_delay is not None:
raise NotImplementedError("Platform {!r} does not support constraining input delay "
"for FFSynchronizer".format(platform))
m = Module()
flops = [Signal(self.i.shape(), name="stage{}".format(index),
reset=self._reset, reset_less=self._reset_less)
@ -111,13 +121,16 @@ class ResetSynchronizer(Elaboratable):
stages : int, >=2
Number of synchronization stages between input and output. The lowest safe number is 2,
with higher numbers reducing MTBF further, at the cost of increased deassertion latency.
max_input_delay : None or float
Maximum delay from the input signal's clock to the first synchronization stage.
If specified and the platform does not support it, elaboration will fail.
Platform override
-----------------
Define the ``get_reset_sync`` platform method to override the implementation of
:class:`ResetSynchronizer`, e.g. to instantiate library cells directly.
"""
def __init__(self, arst, *, domain="sync", stages=2):
def __init__(self, arst, *, domain="sync", stages=2, max_input_delay=None):
_check_stages(stages)
self.arst = arst
@ -125,10 +138,16 @@ class ResetSynchronizer(Elaboratable):
self._domain = domain
self._stages = stages
self._max_input_delay = None
def elaborate(self, platform):
if hasattr(platform, "get_reset_sync"):
return platform.get_reset_sync(self)
if self._max_input_delay is not None:
raise NotImplementedError("Platform {!r} does not support constraining input delay "
"for ResetSynchronizer".format(platform))
m = Module()
m.domains += ClockDomain("reset_sync", async_reset=True, local=True)
flops = [Signal(1, name="stage{}".format(index), reset=1)