fhdl: cd_name→domain.
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whitequark
parent
c5087edfa5
commit
f4340c19bb
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@ -402,8 +402,8 @@ def convert_fragment(builder, fragment, name, top, clock_domains):
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# Register all signals driven in the current fragment. This must be done first, as it
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# affects further codegen; e.g. whether sig$next signals will be generated and used.
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for cd_name, signal in fragment.iter_drivers():
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xformer.add_driven(signal, sync=cd_name is not None)
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for domain, signal in fragment.iter_drivers():
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xformer.add_driven(signal, sync=domain is not None)
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# Register all signals used as ports in the current fragment. The wires are lazily
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# generated, so registering ports eagerly ensures they get correct direction qualifiers.
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@ -412,8 +412,8 @@ def convert_fragment(builder, fragment, name, top, clock_domains):
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# Transform all clocks clocks and resets eagerly and outside of any hierarchy, to make
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# sure they get sensible (non-prefixed) names. This does not affect semantics.
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for cd_name, _ in fragment.iter_sync():
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cd = clock_domains[cd_name]
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for domain, _ in fragment.iter_sync():
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cd = clock_domains[domain]
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xformer(cd.clk)
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xformer(cd.rst)
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@ -433,8 +433,8 @@ def convert_fragment(builder, fragment, name, top, clock_domains):
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with process.case() as case:
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# For every signal in comb domain, assign \sig$next to the reset value.
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# For every signal in sync domains, assign \sig$next to the current value (\sig).
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for cd_name, signal in fragment.iter_drivers():
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if cd_name is None:
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for domain, signal in fragment.iter_drivers():
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if domain is None:
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prev_value = xformer(ast.Const(signal.reset, signal.nbits))
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else:
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prev_value = xformer(signal)
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@ -472,7 +472,7 @@ def convert_fragment(builder, fragment, name, top, clock_domains):
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# as the \init reg attribute) to the reset value. Note that this assigns \sig,
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# not \sig$next.
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with process.sync("init") as sync:
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for cd_name, signal in fragment.iter_sync():
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for domain, signal in fragment.iter_sync():
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sync.update(xformer(signal),
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xformer(ast.Const(signal.reset, signal.nbits)))
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@ -480,17 +480,17 @@ def convert_fragment(builder, fragment, name, top, clock_domains):
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# however, differs between domains: for comb domains, it is `always`, for sync domains
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# with sync reset, it is `posedge clk`, for sync domains with async rest it is
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# `posedge clk or posedge rst`.
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for cd_name, signals in fragment.iter_domains():
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for domain, signals in fragment.iter_domains():
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triggers = []
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if cd_name is None:
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if domain is None:
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triggers.append(("always",))
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elif cd_name in clock_domains:
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cd = clock_domains[cd_name]
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elif domain in clock_domains:
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cd = clock_domains[domain]
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triggers.append(("posedge", xformer(cd.clk)))
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if cd.async_reset:
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triggers.append(("posedge", xformer(cd.rst)))
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else:
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raise ValueError("Clock domain {} not found in design".format(cd_name))
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raise ValueError("Clock domain {} not found in design".format(domain))
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for trigger in triggers:
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with process.sync(*trigger) as sync:
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@ -29,7 +29,7 @@ class _CompatModuleProxy:
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class _CompatModuleComb(_CompatModuleProxy):
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@deprecated("instead of `self.comb +=`, use `m.d.comb +=`")
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def __iadd__(self, assigns):
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self._cm._module._add_statement(assigns, cd_name=None, depth=0, compat_mode=True)
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self._cm._module._add_statement(assigns, domain=None, depth=0, compat_mode=True)
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return self
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@ -40,14 +40,14 @@ class _CompatModuleSyncCD:
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@deprecated("instead of `self.sync.<domain> +=`, use `m.d.<domain> +=`")
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def __iadd__(self, assigns):
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self._cm._module._add_statement(assigns, cd_name=self._cd, depth=0, compat_mode=True)
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self._cm._module._add_statement(assigns, domain=self._cd, depth=0, compat_mode=True)
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return self
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class _CompatModuleSync(_CompatModuleProxy):
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@deprecated("instead of `self.sync +=`, use `m.d.sync +=`")
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def __iadd__(self, assigns):
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self._cm._module._add_statement(assigns, cd_name="sync", depth=0, compat_mode=True)
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self._cm._module._add_statement(assigns, domain="sync", depth=0, compat_mode=True)
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return self
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def __getattr__(self, name):
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@ -20,22 +20,22 @@ class _ModuleBuilderProxy:
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class _ModuleBuilderDomain(_ModuleBuilderProxy):
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def __init__(self, builder, depth, cd_name):
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def __init__(self, builder, depth, domain):
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super().__init__(builder, depth)
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self._cd_name = cd_name
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self._domain = domain
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def __iadd__(self, assigns):
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self._builder._add_statement(assigns, cd_name=self._cd_name, depth=self._depth)
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self._builder._add_statement(assigns, domain=self._domain, depth=self._depth)
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return self
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class _ModuleBuilderDomains(_ModuleBuilderProxy):
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def __getattr__(self, name):
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if name == "comb":
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cd_name = None
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domain = None
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else:
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cd_name = name
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return _ModuleBuilderDomain(self._builder, self._depth, cd_name)
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domain = name
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return _ModuleBuilderDomain(self._builder, self._depth, domain)
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def __getitem__(self, name):
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return self.__getattr__(name)
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@ -228,12 +228,12 @@ class Module(_ModuleBuilderRoot):
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self._statements.append(Switch(switch_test, switch_cases))
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def _add_statement(self, assigns, cd_name, depth, compat_mode=False):
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def cd_human_name(cd_name):
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if cd_name is None:
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def _add_statement(self, assigns, domain, depth, compat_mode=False):
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def domain_name(domain):
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if domain is None:
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return "comb"
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else:
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return cd_name
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return domain
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while len(self._ctrl_stack) > self.domain._depth:
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self._pop_ctrl()
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@ -242,17 +242,17 @@ class Module(_ModuleBuilderRoot):
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if not compat_mode and not isinstance(assign, Assign):
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raise SyntaxError(
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"Only assignments may be appended to d.{}"
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.format(cd_human_name(cd_name)))
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.format(domain_name(domain)))
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for signal in assign._lhs_signals():
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if signal not in self._driving:
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self._driving[signal] = cd_name
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elif self._driving[signal] != cd_name:
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self._driving[signal] = domain
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elif self._driving[signal] != domain:
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cd_curr = self._driving[signal]
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raise SyntaxError(
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"Driver-driver conflict: trying to drive {!r} from d.{}, but it is "
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"already driven from d.{}"
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.format(signal, cd_human_name(cd_name), cd_human_name(cd_curr)))
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.format(signal, domain_name(domain), domain_name(cd_curr)))
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self._statements.append(assign)
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@ -273,8 +273,8 @@ class Module(_ModuleBuilderRoot):
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for submodule, name in self._submodules:
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fragment.add_subfragment(submodule.get_fragment(platform), name)
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fragment.add_statements(self._statements)
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for signal, cd_name in self._driving.items():
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fragment.drive(signal, cd_name)
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for signal, domain in self._driving.items():
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fragment.drive(signal, domain)
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return fragment
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get_fragment = lower
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@ -20,28 +20,28 @@ class Fragment:
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def iter_ports(self):
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yield from self.ports
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def drive(self, signal, cd_name=None):
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if cd_name not in self.drivers:
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self.drivers[cd_name] = ValueSet()
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self.drivers[cd_name].add(signal)
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def drive(self, signal, domain=None):
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if domain not in self.drivers:
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self.drivers[domain] = ValueSet()
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self.drivers[domain].add(signal)
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def iter_domains(self):
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yield from self.drivers.items()
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def iter_drivers(self):
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for cd_name, signals in self.drivers.items():
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for domain, signals in self.drivers.items():
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for signal in signals:
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yield cd_name, signal
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yield domain, signal
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def iter_comb(self):
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yield from self.drivers[None]
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def iter_sync(self):
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for cd_name, signals in self.drivers.items():
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if cd_name is None:
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for domain, signals in self.drivers.items():
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if domain is None:
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continue
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for signal in signals:
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yield cd_name, signal
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yield domain, signal
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def add_statements(self, *stmts):
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self.statements += Statement.wrap(stmts)
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@ -55,8 +55,8 @@ class Fragment:
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# (on RHS of statements, or in clock domains).
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self_driven = union(s._lhs_signals() for s in self.statements)
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self_used = union(s._rhs_signals() for s in self.statements)
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for cd_name, _ in self.iter_sync():
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cd = clock_domains[cd_name]
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for domain, _ in self.iter_sync():
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cd = clock_domains[domain]
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self_used.add(cd.clk)
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if cd.rst is not None:
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self_used.add(cd.rst)
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@ -102,9 +102,9 @@ class FragmentTransformer:
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new_fragment.add_statements(fragment.statements)
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def map_drivers(self, fragment, new_fragment):
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for cd_name, signals in fragment.iter_domains():
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for domain, signals in fragment.iter_domains():
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for signal in signals:
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new_fragment.drive(signal, cd_name)
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new_fragment.drive(signal, domain)
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def on_fragment(self, fragment):
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new_fragment = Fragment()
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@ -134,11 +134,11 @@ class DomainRenamer(FragmentTransformer, ValueTransformer, StatementTransformer)
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return value
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def map_drivers(self, fragment, new_fragment):
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for cd_name, signals in fragment.iter_domains():
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if cd_name in self.domains:
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cd_name = self.domains[cd_name]
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for domain, signals in fragment.iter_domains():
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if domain in self.domains:
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domain = self.domains[domain]
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for signal in signals:
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new_fragment.drive(signal, cd_name)
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new_fragment.drive(signal, domain)
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class _ControlInserter(FragmentTransformer):
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@ -149,23 +149,23 @@ class _ControlInserter(FragmentTransformer):
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def on_fragment(self, fragment):
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new_fragment = super().on_fragment(fragment)
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for cd_name, signals in fragment.iter_domains():
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if cd_name is None or cd_name not in self.controls:
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for domain, signals in fragment.iter_domains():
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if domain is None or domain not in self.controls:
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continue
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self._insert_control(new_fragment, cd_name, signals)
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self._insert_control(new_fragment, domain, signals)
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return new_fragment
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def _insert_control(self, fragment, cd_name, signals):
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def _insert_control(self, fragment, domain, signals):
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raise NotImplementedError # :nocov:
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class ResetInserter(_ControlInserter):
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def _insert_control(self, fragment, cd_name, signals):
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def _insert_control(self, fragment, domain, signals):
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stmts = [s.eq(Const(s.reset, s.nbits)) for s in signals if not s.reset_less]
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fragment.add_statements(Switch(self.controls[cd_name], {1: stmts}))
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fragment.add_statements(Switch(self.controls[domain], {1: stmts}))
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class CEInserter(_ControlInserter):
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def _insert_control(self, fragment, cd_name, signals):
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def _insert_control(self, fragment, domain, signals):
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stmts = [s.eq(s) for s in signals]
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fragment.add_statements(Switch(self.controls[cd_name], {0: stmts}))
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fragment.add_statements(Switch(self.controls[domain], {0: stmts}))
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