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fhdl: cd_name→domain.

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This commit is contained in:
whitequark 2018-12-13 10:15:01 +00:00
parent c5087edfa5
commit f4340c19bb
5 changed files with 56 additions and 56 deletions
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32
nmigen/fhdl/dsl.py
View file

@ -20,22 +20,22 @@ class _ModuleBuilderProxy:
class _ModuleBuilderDomain(_ModuleBuilderProxy):
def __init__(self, builder, depth, cd_name):
def __init__(self, builder, depth, domain):
super().__init__(builder, depth)
self._cd_name = cd_name
self._domain = domain
def __iadd__(self, assigns):
self._builder._add_statement(assigns, cd_name=self._cd_name, depth=self._depth)
self._builder._add_statement(assigns, domain=self._domain, depth=self._depth)
return self
class _ModuleBuilderDomains(_ModuleBuilderProxy):
def __getattr__(self, name):
if name == "comb":
cd_name = None
domain = None
else:
cd_name = name
return _ModuleBuilderDomain(self._builder, self._depth, cd_name)
domain = name
return _ModuleBuilderDomain(self._builder, self._depth, domain)
def __getitem__(self, name):
return self.__getattr__(name)
@ -228,12 +228,12 @@ class Module(_ModuleBuilderRoot):
self._statements.append(Switch(switch_test, switch_cases))
def _add_statement(self, assigns, cd_name, depth, compat_mode=False):
def cd_human_name(cd_name):
if cd_name is None:
def _add_statement(self, assigns, domain, depth, compat_mode=False):
def domain_name(domain):
if domain is None:
return "comb"
else:
return cd_name
return domain
while len(self._ctrl_stack) > self.domain._depth:
self._pop_ctrl()
@ -242,17 +242,17 @@ class Module(_ModuleBuilderRoot):
if not compat_mode and not isinstance(assign, Assign):
raise SyntaxError(
"Only assignments may be appended to d.{}"
.format(cd_human_name(cd_name)))
.format(domain_name(domain)))
for signal in assign._lhs_signals():
if signal not in self._driving:
self._driving[signal] = cd_name
elif self._driving[signal] != cd_name:
self._driving[signal] = domain
elif self._driving[signal] != domain:
cd_curr = self._driving[signal]
raise SyntaxError(
"Driver-driver conflict: trying to drive {!r} from d.{}, but it is "
"already driven from d.{}"
.format(signal, cd_human_name(cd_name), cd_human_name(cd_curr)))
.format(signal, domain_name(domain), domain_name(cd_curr)))
self._statements.append(assign)
@ -273,8 +273,8 @@ class Module(_ModuleBuilderRoot):
for submodule, name in self._submodules:
fragment.add_subfragment(submodule.get_fragment(platform), name)
fragment.add_statements(self._statements)
for signal, cd_name in self._driving.items():
fragment.drive(signal, cd_name)
for signal, domain in self._driving.items():
fragment.drive(signal, domain)
return fragment
get_fragment = lower

22
nmigen/fhdl/ir.py
View file

@ -20,28 +20,28 @@ class Fragment:
def iter_ports(self):
yield from self.ports
def drive(self, signal, cd_name=None):
if cd_name not in self.drivers:
self.drivers[cd_name] = ValueSet()
self.drivers[cd_name].add(signal)
def drive(self, signal, domain=None):
if domain not in self.drivers:
self.drivers[domain] = ValueSet()
self.drivers[domain].add(signal)
def iter_domains(self):
yield from self.drivers.items()
def iter_drivers(self):
for cd_name, signals in self.drivers.items():
for domain, signals in self.drivers.items():
for signal in signals:
yield cd_name, signal
yield domain, signal
def iter_comb(self):
yield from self.drivers[None]
def iter_sync(self):
for cd_name, signals in self.drivers.items():
if cd_name is None:
for domain, signals in self.drivers.items():
if domain is None:
continue
for signal in signals:
yield cd_name, signal
yield domain, signal
def add_statements(self, *stmts):
self.statements += Statement.wrap(stmts)
@ -55,8 +55,8 @@ class Fragment:
# (on RHS of statements, or in clock domains).
self_driven = union(s._lhs_signals() for s in self.statements)
self_used = union(s._rhs_signals() for s in self.statements)
for cd_name, _ in self.iter_sync():
cd = clock_domains[cd_name]
for domain, _ in self.iter_sync():
cd = clock_domains[domain]
self_used.add(cd.clk)
if cd.rst is not None:
self_used.add(cd.rst)

28
nmigen/fhdl/xfrm.py
View file

@ -102,9 +102,9 @@ class FragmentTransformer:
new_fragment.add_statements(fragment.statements)
def map_drivers(self, fragment, new_fragment):
for cd_name, signals in fragment.iter_domains():
for domain, signals in fragment.iter_domains():
for signal in signals:
new_fragment.drive(signal, cd_name)
new_fragment.drive(signal, domain)
def on_fragment(self, fragment):
new_fragment = Fragment()
@ -134,11 +134,11 @@ class DomainRenamer(FragmentTransformer, ValueTransformer, StatementTransformer)
return value
def map_drivers(self, fragment, new_fragment):
for cd_name, signals in fragment.iter_domains():
if cd_name in self.domains:
cd_name = self.domains[cd_name]
for domain, signals in fragment.iter_domains():
if domain in self.domains:
domain = self.domains[domain]
for signal in signals:
new_fragment.drive(signal, cd_name)
new_fragment.drive(signal, domain)
class _ControlInserter(FragmentTransformer):
@ -149,23 +149,23 @@ class _ControlInserter(FragmentTransformer):
def on_fragment(self, fragment):
new_fragment = super().on_fragment(fragment)
for cd_name, signals in fragment.iter_domains():
if cd_name is None or cd_name not in self.controls:
for domain, signals in fragment.iter_domains():
if domain is None or domain not in self.controls:
continue
self._insert_control(new_fragment, cd_name, signals)
self._insert_control(new_fragment, domain, signals)
return new_fragment
def _insert_control(self, fragment, cd_name, signals):
def _insert_control(self, fragment, domain, signals):
raise NotImplementedError # :nocov:
class ResetInserter(_ControlInserter):
def _insert_control(self, fragment, cd_name, signals):
def _insert_control(self, fragment, domain, signals):
stmts = [s.eq(Const(s.reset, s.nbits)) for s in signals if not s.reset_less]
fragment.add_statements(Switch(self.controls[cd_name], {1: stmts}))
fragment.add_statements(Switch(self.controls[domain], {1: stmts}))
class CEInserter(_ControlInserter):
def _insert_control(self, fragment, cd_name, signals):
def _insert_control(self, fragment, domain, signals):
stmts = [s.eq(s) for s in signals]
fragment.add_statements(Switch(self.controls[cd_name], {0: stmts}))
fragment.add_statements(Switch(self.controls[domain], {0: stmts}))