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lib.cdc: add ResetSynchronizer.

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This commit is contained in:
whitequark 2019-01-26 18:07:59 +00:00
parent e74dbc3377
commit f44ca291c1
2 changed files with 68 additions and 2 deletions
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43
nmigen/test/test_lib_cdc.py
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@ -1,5 +1,7 @@
from .tools import *
from ..hdl.ast import *
from ..hdl.cd import *
from ..hdl.dsl import *
from ..back.pysim import *
from ..lib.cdc import *
@ -23,7 +25,7 @@ class MultiRegTestCase(FHDLTestCase):
sim.add_process(process)
sim.run()
def test_basic(self):
def test_reset_value(self):
i = Signal(reset=1)
o = Signal()
frag = MultiReg(i, o, reset=1)
@ -40,3 +42,42 @@ class MultiRegTestCase(FHDLTestCase):
self.assertEqual((yield o), 0)
sim.add_process(process)
sim.run()
class ResetSynchronizerTestCase(FHDLTestCase):
def test_basic(self):
arst = Signal()
m = Module()
m.domains += ClockDomain("sync")
m.submodules += ResetSynchronizer(arst)
s = Signal(reset=1)
m.d.sync += s.eq(0)
with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
sim.add_clock(1e-6)
def process():
# initial reset
self.assertEqual((yield s), 1)
yield Tick(); yield Delay(1e-8)
self.assertEqual((yield s), 1)
yield Tick(); yield Delay(1e-8)
self.assertEqual((yield s), 1)
yield Tick(); yield Delay(1e-8)
self.assertEqual((yield s), 0)
yield Tick(); yield Delay(1e-8)
yield arst.eq(1)
yield Delay(1e-8)
self.assertEqual((yield s), 1)
yield Tick(); yield Delay(1e-8)
self.assertEqual((yield s), 1)
yield arst.eq(0)
yield Tick(); yield Delay(1e-8)
self.assertEqual((yield s), 1)
yield Tick(); yield Delay(1e-8)
self.assertEqual((yield s), 1)
yield Tick(); yield Delay(1e-8)
self.assertEqual((yield s), 0)
yield Tick(); yield Delay(1e-8)
sim.add_process(process)
sim.run()