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sim: Add tests for memory access.

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Wanda 2024-02-03 17:16:33 +01:00 committed by Catherine
parent 83a9149c4c
commit f4daf74634
1 changed files with 34 additions and 0 deletions
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34
tests/test_sim.py
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@ -994,6 +994,40 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
sim.add_clock(1e-6)
sim.add_testbench(process)
def test_memory_access(self):
self.setUp_memory()
with self.assertSimulation(self.m) as sim:
def process():
self.assertEqual((yield self.memory[1]), 0x55)
self.assertEqual((yield self.memory[Const(1)]), 0x55)
self.assertEqual((yield self.memory[Const(2)]), 0x00)
yield self.memory[Const(1)].eq(Const(0x33))
self.assertEqual((yield self.memory[Const(1)]), 0x33)
yield self.wrport.addr.eq(3)
yield self.wrport.data.eq(0x22)
yield self.wrport.en.eq(1)
self.assertEqual((yield self.memory[Const(3)]), 0)
yield Tick()
self.assertEqual((yield self.memory[Const(3)]), 0x22)
sim.add_clock(1e-6)
sim.add_testbench(process)
def test_memory_access_sync(self):
self.setUp_memory()
with self.assertSimulation(self.m) as sim:
def process():
self.assertEqual((yield self.memory[1]), 0x55)
self.assertEqual((yield self.memory[Const(1)]), 0x55)
self.assertEqual((yield self.memory[Const(2)]), 0x00)
yield self.memory[Const(1)].eq(Const(0x33))
self.assertEqual((yield self.memory[Const(1)]), 0x55)
yield
self.assertEqual((yield self.memory[Const(1)]), 0x33)
sim.add_clock(1e-6)
sim.add_sync_process(process)
def test_vcd_wrong_nonzero_time(self):
s = Signal()
m = Module()