lib.io, build.res: Make Pin and related objects interfaces.
Fixes #1040.
This commit is contained in:
Wanda
Catherine
parent
c30585b47b
commit
f524dd041a
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@ -1,10 +1,6 @@
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from collections import OrderedDict
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import warnings
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from ..hdl._ast import *
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with warnings.catch_warnings():
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warnings.filterwarnings(action="ignore", category=DeprecationWarning)
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from ..hdl.rec import *
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from ..lib.io import *
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from ..lib import wiring
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@ -106,7 +102,7 @@ class ResourceManager:
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.format(subsignal.ios[0], xdr))
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return dir, xdr
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def resolve(resource, dir, xdr, name, attrs):
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def resolve(resource, dir, xdr, path, attrs):
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for attr_key, attr_value in attrs.items():
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if hasattr(attr_value, "__call__"):
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attr_value = attr_value(self)
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@ -117,18 +113,21 @@ class ResourceManager:
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attrs[attr_key] = attr_value
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if isinstance(resource.ios[0], Subsignal):
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fields = OrderedDict()
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members = OrderedDict()
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sig_members = OrderedDict()
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for sub in resource.ios:
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fields[sub.name] = resolve(sub, dir[sub.name], xdr[sub.name],
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name=f"{name}__{sub.name}",
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member = resolve(sub, dir[sub.name], xdr[sub.name],
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path=path + (sub.name,),
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attrs={**attrs, **sub.attrs})
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rec = Record([
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(f_name, f.layout) for (f_name, f) in fields.items()
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], fields=fields, name=name)
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rec.signature = wiring.Signature({
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f_name: wiring.Out(f.signature) for (f_name, f) in fields.items()
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})
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return rec
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members[sub.name] = member
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sig_members[sub.name] = wiring.Out(member.signature)
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signature = wiring.Signature(sig_members)
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# Provide members ourselves instead of having the constructor
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# create ones for us.
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intf = object.__new__(wiring.PureInterface)
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intf.signature = signature
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intf.__dict__.update(members)
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return intf
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elif isinstance(resource.ios[0], (Pins, DiffPairs)):
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phys = resource.ios[0]
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@ -137,34 +136,30 @@ class ResourceManager:
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# ignore it as well.
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if isinstance(phys, Pins):
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phys_names = phys.names
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port = Record([("io", len(phys))], name=name)
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port.signature = wiring.Signature({"io": wiring.In(len(phys))})
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port = wiring.Signature({"io": wiring.In(len(phys))}).create(path=path)
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if isinstance(phys, DiffPairs):
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phys_names = []
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rec_members = []
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sig_members = {}
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if not self.should_skip_port_component(None, attrs, "p"):
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phys_names += phys.p.names
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rec_members.append(("p", len(phys)))
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sig_members["p"] = wiring.In(len(phys))
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if not self.should_skip_port_component(None, attrs, "n"):
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phys_names += phys.n.names
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rec_members.append(("n", len(phys)))
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sig_members["n"] = wiring.In(len(phys))
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port = Record(rec_members, name=name)
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port.signature = wiring.Signature(sig_members)
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port = wiring.Signature(sig_members).create(path=path)
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if dir == "-":
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pin = None
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else:
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pin = wiring.flipped(Pin(len(phys), dir, xdr=xdr, name=name))
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pin = wiring.flipped(Pin(len(phys), dir, xdr=xdr, path=path))
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for phys_name in phys_names:
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if phys_name in self._phys_reqd:
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raise ResourceError("Resource component {} uses physical pin {}, but it "
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"is already used by resource component {} that was "
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"requested earlier"
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.format(name, phys_name, self._phys_reqd[phys_name]))
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self._phys_reqd[phys_name] = name
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.format(".".join(path), phys_name,
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".".join(self._phys_reqd[phys_name])))
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self._phys_reqd[phys_name] = path
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self._ports.append((resource, pin, port, attrs))
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@ -178,7 +173,7 @@ class ResourceManager:
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value = resolve(resource,
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*merge_options(resource, dir, xdr),
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name=f"{resource.name}_{resource.number}",
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path=(f"{resource.name}_{resource.number}",),
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attrs=resource.attrs)
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self._requested[resource.name, resource.number] = value
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return value
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@ -1,74 +1,18 @@
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import warnings
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from .. import *
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with warnings.catch_warnings():
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warnings.filterwarnings(action="ignore", category=DeprecationWarning)
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from ..hdl.rec import *
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from ..lib.wiring import In, Out, Signature, flipped, FlippedInterface
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from ..lib import wiring
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from ..lib.wiring import In, Out
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__all__ = ["pin_layout", "Pin"]
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__all__ = ["Pin"]
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def _pin_signature(width, dir, xdr=0):
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if not isinstance(width, int) or width < 0:
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raise TypeError("Width must be a non-negative integer, not {!r}"
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.format(width))
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if dir not in ("i", "o", "oe", "io"):
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raise TypeError("Direction must be one of \"i\", \"o\", \"io\", or \"oe\", not {!r}"""
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.format(dir))
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if not isinstance(xdr, int) or xdr < 0:
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raise TypeError("Gearing ratio must be a non-negative integer, not {!r}"
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.format(xdr))
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members = {}
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if dir in ("i", "io"):
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if xdr > 0:
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members["i_clk"] = In(1)
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if xdr > 2:
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members["i_fclk"] = In(1)
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if xdr in (0, 1):
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members["i"] = In(width)
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else:
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for n in range(xdr):
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members[f"i{n}"] = In(width)
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if dir in ("o", "oe", "io"):
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if xdr > 0:
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members["o_clk"] = Out(1)
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if xdr > 2:
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members["o_fclk"] = Out(1)
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if xdr in (0, 1):
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members["o"] = Out(width)
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else:
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for n in range(xdr):
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members[f"o{n}"] = Out(width)
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if dir in ("oe", "io"):
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members["oe"] = Out(1)
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return Signature(members)
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def pin_layout(width, dir, xdr=0):
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"""
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Layout of the platform interface of a pin or several pins, which may be used inside
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user-defined records.
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See :class:`Pin` for details.
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"""
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fields = []
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for name, member in _pin_signature(width, dir, xdr).members.items():
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fields.append((name, member.shape))
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return Layout(fields)
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class Pin(Record):
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class Pin(wiring.PureInterface):
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"""
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An interface to an I/O buffer or a group of them that provides uniform access to input, output,
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or tristate buffers that may include a 1:n gearbox. (A 1:2 gearbox is typically called "DDR".)
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A :class:`Pin` is identical to a :class:`Record` that uses the corresponding :meth:`pin_layout`
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except that it allows accessing the parameters like ``width`` as attributes. It is legal to use
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a plain :class:`Record` anywhere a :class:`Pin` is used, provided that these attributes are
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not necessary.
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This is an interface object using :class:`Pin.Signature` as its signature. The signature flows
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are defined from the point of view of a component that drives the I/O buffer.
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Parameters
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----------
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@ -87,8 +31,8 @@ class Pin(Record):
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are present instead, where ``N in range(0, N)``. For example, if ``xdr=2``, the I/O buffer
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is DDR; the signal ``i0`` reflects the value at the rising edge, and the signal ``i1``
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reflects the value at the falling edge.
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name : str
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Name of the underlying record.
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path : tuple of str
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As in :class:`PureInterface`, used to name the created signals.
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Attributes
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----------
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@ -119,23 +63,76 @@ class Pin(Record):
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cannot change direction more than once per cycle, so at most one output enable signal
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is present.
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"""
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def __init__(self, width, dir, *, xdr=0, name=None, src_loc_at=0):
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self.width = width
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self.dir = dir
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self.xdr = xdr
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super().__init__(pin_layout(self.width, self.dir, self.xdr),
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name=name, src_loc_at=src_loc_at + 1)
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class Signature(wiring.Signature):
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"""A signature for :class:`Pin`. The parameters are as defined on the ``Pin`` class,
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and are accessible as attributes.
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"""
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def __init__(self, width, dir, *, xdr=0):
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if not isinstance(width, int) or width < 0:
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raise TypeError("Width must be a non-negative integer, not {!r}"
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.format(width))
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if dir not in ("i", "o", "oe", "io"):
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raise TypeError("Direction must be one of \"i\", \"o\", \"io\", or \"oe\", not {!r}"""
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.format(dir))
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if not isinstance(xdr, int) or xdr < 0:
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raise TypeError("Gearing ratio must be a non-negative integer, not {!r}"
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.format(xdr))
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self.width = width
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self.dir = dir
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self.xdr = xdr
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members = {}
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if dir in ("i", "io"):
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if xdr > 0:
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members["i_clk"] = Out(1)
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if xdr > 2:
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members["i_fclk"] = Out(1)
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if xdr in (0, 1):
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members["i"] = In(width)
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else:
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for n in range(xdr):
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members[f"i{n}"] = In(width)
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if dir in ("o", "oe", "io"):
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if xdr > 0:
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members["o_clk"] = Out(1)
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if xdr > 2:
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members["o_fclk"] = Out(1)
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if xdr in (0, 1):
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members["o"] = Out(width)
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else:
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for n in range(xdr):
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members[f"o{n}"] = Out(width)
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if dir in ("oe", "io"):
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members["oe"] = Out(1)
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super().__init__(members)
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def __eq__(self, other):
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return (type(self) is type(other) and
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self.width == other.width and
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self.dir == other.dir and
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self.xdr == other.xdr)
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def create(self, *, path=None, src_loc_at=0):
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return Pin(self.width, self.dir, xdr=self.xdr, path=path, src_loc_at=1 + src_loc_at)
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def __init__(self, width, dir, *, xdr=0, name=None, path=None, src_loc_at=0):
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if name is not None:
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if path is None:
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raise ValueError("Cannot pass both name and path")
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path = (name,)
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signature = Pin.Signature(width, dir, xdr=xdr)
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super().__init__(signature, path=path, src_loc_at=src_loc_at + 1)
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@property
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def signature(self):
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return _pin_signature(self.width, self.dir, self.xdr)
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def width(self):
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return self.signature.width
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def eq(self, other):
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first_field, _, _ = next(iter(Pin(1, dir="o").layout))
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warnings.warn(f"`pin.eq(...)` is deprecated; use `pin.{first_field}.eq(...)` here",
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DeprecationWarning, stacklevel=2)
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if isinstance(self, FlippedInterface):
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return Record.eq(flipped(self), other)
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else:
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return Record.eq(self, other)
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@property
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def dir(self):
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return self.signature.dir
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@property
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def xdr(self):
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return self.signature.xdr
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@ -64,7 +64,7 @@ class ResourceManagerTestCase(FHDLTestCase):
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user_led = self.cm.request("user_led", 0)
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self.assertIsInstance(flipped(user_led), Pin)
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self.assertEqual(user_led.name, "user_led_0")
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self.assertEqual(user_led.o.name, "user_led_0__o")
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self.assertEqual(user_led.width, 1)
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self.assertEqual(user_led.dir, "o")
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@ -77,12 +77,14 @@ class ResourceManagerTestCase(FHDLTestCase):
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def test_request_with_dir(self):
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i2c = self.cm.request("i2c", 0, dir={"sda": "o"})
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self.assertIsInstance(i2c, Record)
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self.assertIsInstance(i2c.sda, Pin)
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self.assertIsInstance(i2c, PureInterface)
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self.assertTrue(i2c.signature.is_compliant(i2c))
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self.assertIsInstance(flipped(i2c.sda), Pin)
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self.assertEqual(i2c.sda.dir, "o")
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def test_request_tristate(self):
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i2c = self.cm.request("i2c", 0)
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self.assertTrue(i2c.signature.is_compliant(i2c))
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self.assertEqual(i2c.sda.dir, "io")
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ports = list(self.cm.iter_ports())
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@ -92,11 +94,11 @@ class ResourceManagerTestCase(FHDLTestCase):
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self.assertEqual(ports[1].width, 1)
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scl_info, sda_info = self.cm.iter_single_ended_pins()
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self.assertIs(flipped(scl_info[0]), i2c.scl)
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self.assertIs(scl_info[0], i2c.scl)
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self.assertIs(scl_info[1].io, scl)
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self.assertEqual(scl_info[2], {})
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self.assertEqual(scl_info[3], False)
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self.assertIs(flipped(sda_info[0]), i2c.sda)
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self.assertIs(sda_info[0], i2c.sda)
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self.assertIs(sda_info[1].io, sda)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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@ -315,12 +317,3 @@ class ResourceManagerTestCase(FHDLTestCase):
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(r"^Cannot add clock constraint on \(sig clk100_0__i\), which is already "
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r"constrained to 100000000\.0 Hz$")):
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self.cm.add_clock_constraint(clk100.i, 1e6)
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def test_eq_deprecation(self):
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user_led = self.cm.request("user_led", 0)
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m = Module()
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with self.assertWarns(DeprecationWarning):
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m.d.sync += user_led.eq(1)
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p = Pin(4, "o")
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with self.assertWarns(DeprecationWarning):
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m.d.sync += p.eq(1)
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@ -1,207 +1,201 @@
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import warnings
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from amaranth.hdl import *
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with warnings.catch_warnings():
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warnings.filterwarnings(action="ignore", category=DeprecationWarning)
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from amaranth.hdl.rec import *
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from amaranth.sim import *
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from amaranth.lib.io import *
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from amaranth.lib.wiring import *
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from .utils import *
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class PinLayoutTestCase(FHDLTestCase):
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def assertLayoutEqual(self, layout, expected):
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casted_layout = {}
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for name, (shape, dir) in layout.items():
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casted_layout[name] = (Shape.cast(shape), dir)
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self.assertEqual(casted_layout, expected)
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class PinSignatureTestCase(FHDLTestCase):
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def assertSignatureEqual(self, signature, expected):
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self.assertEqual(signature.members, Signature(expected).members)
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class PinLayoutCombTestCase(PinLayoutTestCase):
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def test_pin_layout_i(self):
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layout_1 = pin_layout(1, dir="i")
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self.assertLayoutEqual(layout_1.fields, {
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"i": (unsigned(1), DIR_NONE),
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class PinSignatureCombTestCase(PinSignatureTestCase):
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def test_signature_i(self):
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sig_1 = Pin.Signature(1, dir="i")
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self.assertSignatureEqual(sig_1, {
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"i": In(1),
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})
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layout_2 = pin_layout(2, dir="i")
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self.assertLayoutEqual(layout_2.fields, {
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"i": (unsigned(2), DIR_NONE),
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sig_2 = Pin.Signature(2, dir="i")
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self.assertSignatureEqual(sig_2, {
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"i": In(2),
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})
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def test_pin_layout_o(self):
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layout_1 = pin_layout(1, dir="o")
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self.assertLayoutEqual(layout_1.fields, {
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"o": (unsigned(1), DIR_NONE),
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def test_signature_o(self):
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sig_1 = Pin.Signature(1, dir="o")
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self.assertSignatureEqual(sig_1, {
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"o": Out(1),
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})
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layout_2 = pin_layout(2, dir="o")
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self.assertLayoutEqual(layout_2.fields, {
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"o": (unsigned(2), DIR_NONE),
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sig_2 = Pin.Signature(2, dir="o")
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self.assertSignatureEqual(sig_2, {
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"o": Out(2),
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})
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def test_pin_layout_oe(self):
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layout_1 = pin_layout(1, dir="oe")
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self.assertLayoutEqual(layout_1.fields, {
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"o": (unsigned(1), DIR_NONE),
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"oe": (unsigned(1), DIR_NONE),
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def test_signature_oe(self):
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sig_1 = Pin.Signature(1, dir="oe")
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self.assertSignatureEqual(sig_1, {
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"o": Out(1),
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"oe": Out(1),
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})
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layout_2 = pin_layout(2, dir="oe")
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self.assertLayoutEqual(layout_2.fields, {
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"o": (unsigned(2), DIR_NONE),
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"oe": (unsigned(1), DIR_NONE),
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sig_2 = Pin.Signature(2, dir="oe")
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self.assertSignatureEqual(sig_2, {
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"o": Out(2),
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"oe": Out(1),
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})
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def test_pin_layout_io(self):
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layout_1 = pin_layout(1, dir="io")
|
||||
self.assertLayoutEqual(layout_1.fields, {
|
||||
"i": (unsigned(1), DIR_NONE),
|
||||
"o": (unsigned(1), DIR_NONE),
|
||||
"oe": (unsigned(1), DIR_NONE),
|
||||
def test_signature_io(self):
|
||||
sig_1 = Pin.Signature(1, dir="io")
|
||||
self.assertSignatureEqual(sig_1, {
|
||||
"i": In(1),
|
||||
"o": Out(1),
|
||||
"oe": Out(1),
|
||||
})
|
||||
|
||||
layout_2 = pin_layout(2, dir="io")
|
||||
self.assertLayoutEqual(layout_2.fields, {
|
||||
"i": (unsigned(2), DIR_NONE),
|
||||
"o": (unsigned(2), DIR_NONE),
|
||||
"oe": (unsigned(1), DIR_NONE),
|
||||
sig_2 = Pin.Signature(2, dir="io")
|
||||
self.assertSignatureEqual(sig_2, {
|
||||
"i": In(2),
|
||||
"o": Out(2),
|
||||
"oe": Out(1),
|
||||
})
|
||||
|
||||
|
||||
class PinLayoutSDRTestCase(PinLayoutTestCase):
|
||||
def test_pin_layout_i(self):
|
||||
layout_1 = pin_layout(1, dir="i", xdr=1)
|
||||
self.assertLayoutEqual(layout_1.fields, {
|
||||
"i_clk": (unsigned(1), DIR_NONE),
|
||||
"i": (unsigned(1), DIR_NONE),
|
||||
class PinSignatureSDRTestCase(PinSignatureTestCase):
|
||||
def test_signature_i(self):
|
||||
sig_1 = Pin.Signature(1, dir="i", xdr=1)
|
||||
self.assertSignatureEqual(sig_1, {
|
||||
"i_clk": Out(1),
|
||||
"i": In(1),
|
||||
})
|
||||
|
||||
layout_2 = pin_layout(2, dir="i", xdr=1)
|
||||
self.assertLayoutEqual(layout_2.fields, {
|
||||
"i_clk": (unsigned(1), DIR_NONE),
|
||||
"i": (unsigned(2), DIR_NONE),
|
||||
sig_2 = Pin.Signature(2, dir="i", xdr=1)
|
||||
self.assertSignatureEqual(sig_2, {
|
||||
"i_clk": Out(1),
|
||||
"i": In(2),
|
||||
})
|
||||
|
||||
def test_pin_layout_o(self):
|
||||
layout_1 = pin_layout(1, dir="o", xdr=1)
|
||||
self.assertLayoutEqual(layout_1.fields, {
|
||||
"o_clk": (unsigned(1), DIR_NONE),
|
||||
"o": (unsigned(1), DIR_NONE),
|
||||
def test_signature_o(self):
|
||||
sig_1 = Pin.Signature(1, dir="o", xdr=1)
|
||||
self.assertSignatureEqual(sig_1, {
|
||||
"o_clk": Out(1),
|
||||
"o": Out(1),
|
||||
})
|
||||
|
||||
layout_2 = pin_layout(2, dir="o", xdr=1)
|
||||
self.assertLayoutEqual(layout_2.fields, {
|
||||
"o_clk": (unsigned(1), DIR_NONE),
|
||||
"o": (unsigned(2), DIR_NONE),
|
||||
sig_2 = Pin.Signature(2, dir="o", xdr=1)
|
||||
self.assertSignatureEqual(sig_2, {
|
||||
"o_clk": Out(1),
|
||||
"o": Out(2),
|
||||
})
|
||||
|
||||
def test_pin_layout_oe(self):
|
||||
layout_1 = pin_layout(1, dir="oe", xdr=1)
|
||||
self.assertLayoutEqual(layout_1.fields, {
|
||||
"o_clk": (unsigned(1), DIR_NONE),
|
||||
"o": (unsigned(1), DIR_NONE),
|
||||
"oe": (unsigned(1), DIR_NONE),
|
||||
def test_signature_oe(self):
|
||||
sig_1 = Pin.Signature(1, dir="oe", xdr=1)
|
||||
self.assertSignatureEqual(sig_1, {
|
||||
"o_clk": Out(1),
|
||||
"o": Out(1),
|
||||
"oe": Out(1),
|
||||
})
|
||||
|
||||
layout_2 = pin_layout(2, dir="oe", xdr=1)
|
||||
self.assertLayoutEqual(layout_2.fields, {
|
||||
"o_clk": (unsigned(1), DIR_NONE),
|
||||
"o": (unsigned(2), DIR_NONE),
|
||||
"oe": (unsigned(1), DIR_NONE),
|
||||
sig_2 = Pin.Signature(2, dir="oe", xdr=1)
|
||||
self.assertSignatureEqual(sig_2, {
|
||||
"o_clk": Out(1),
|
||||
"o": Out(2),
|
||||
"oe": Out(1),
|
||||
})
|
||||
|
||||
def test_pin_layout_io(self):
|
||||
layout_1 = pin_layout(1, dir="io", xdr=1)
|
||||
self.assertLayoutEqual(layout_1.fields, {
|
||||
"i_clk": (unsigned(1), DIR_NONE),
|
||||
"i": (unsigned(1), DIR_NONE),
|
||||
"o_clk": (unsigned(1), DIR_NONE),
|
||||
"o": (unsigned(1), DIR_NONE),
|
||||
"oe": (unsigned(1), DIR_NONE),
|
||||
def test_signature_io(self):
|
||||
sig_1 = Pin.Signature(1, dir="io", xdr=1)
|
||||
self.assertSignatureEqual(sig_1, {
|
||||
"i_clk": Out(1),
|
||||
"i": In(1),
|
||||
"o_clk": Out(1),
|
||||
"o": Out(1),
|
||||
"oe": Out(1),
|
||||
})
|
||||
|
||||
layout_2 = pin_layout(2, dir="io", xdr=1)
|
||||
self.assertLayoutEqual(layout_2.fields, {
|
||||
"i_clk": (unsigned(1), DIR_NONE),
|
||||
"i": (unsigned(2), DIR_NONE),
|
||||
"o_clk": (unsigned(1), DIR_NONE),
|
||||
"o": (unsigned(2), DIR_NONE),
|
||||
"oe": (unsigned(1), DIR_NONE),
|
||||
sig_2 = Pin.Signature(2, dir="io", xdr=1)
|
||||
self.assertSignatureEqual(sig_2, {
|
||||
"i_clk": Out(1),
|
||||
"i": In(2),
|
||||
"o_clk": Out(1),
|
||||
"o": Out(2),
|
||||
"oe": Out(1),
|
||||
})
|
||||
|
||||
|
||||
class PinLayoutDDRTestCase(PinLayoutTestCase):
|
||||
def test_pin_layout_i(self):
|
||||
layout_1 = pin_layout(1, dir="i", xdr=2)
|
||||
self.assertLayoutEqual(layout_1.fields, {
|
||||
"i_clk": (unsigned(1), DIR_NONE),
|
||||
"i0": (unsigned(1), DIR_NONE),
|
||||
"i1": (unsigned(1), DIR_NONE),
|
||||
class PinSignatureDDRTestCase(PinSignatureTestCase):
|
||||
def test_signature_i(self):
|
||||
sig_1 = Pin.Signature(1, dir="i", xdr=2)
|
||||
self.assertSignatureEqual(sig_1, {
|
||||
"i_clk": Out(1),
|
||||
"i0": In(1),
|
||||
"i1": In(1),
|
||||
})
|
||||
|
||||
layout_2 = pin_layout(2, dir="i", xdr=2)
|
||||
self.assertLayoutEqual(layout_2.fields, {
|
||||
"i_clk": (unsigned(1), DIR_NONE),
|
||||
"i0": (unsigned(2), DIR_NONE),
|
||||
"i1": (unsigned(2), DIR_NONE),
|
||||
sig_2 = Pin.Signature(2, dir="i", xdr=2)
|
||||
self.assertSignatureEqual(sig_2, {
|
||||
"i_clk": Out(1),
|
||||
"i0": In(2),
|
||||
"i1": In(2),
|
||||
})
|
||||
|
||||
def test_pin_layout_o(self):
|
||||
layout_1 = pin_layout(1, dir="o", xdr=2)
|
||||
self.assertLayoutEqual(layout_1.fields, {
|
||||
"o_clk": (unsigned(1), DIR_NONE),
|
||||
"o0": (unsigned(1), DIR_NONE),
|
||||
"o1": (unsigned(1), DIR_NONE),
|
||||
def test_signature_o(self):
|
||||
sig_1 = Pin.Signature(1, dir="o", xdr=2)
|
||||
self.assertSignatureEqual(sig_1, {
|
||||
"o_clk": Out(1),
|
||||
"o0": Out(1),
|
||||
"o1": Out(1),
|
||||
})
|
||||
|
||||
layout_2 = pin_layout(2, dir="o", xdr=2)
|
||||
self.assertLayoutEqual(layout_2.fields, {
|
||||
"o_clk": (unsigned(1), DIR_NONE),
|
||||
"o0": (unsigned(2), DIR_NONE),
|
||||
"o1": (unsigned(2), DIR_NONE),
|
||||
sig_2 = Pin.Signature(2, dir="o", xdr=2)
|
||||
self.assertSignatureEqual(sig_2, {
|
||||
"o_clk": Out(1),
|
||||
"o0": Out(2),
|
||||
"o1": Out(2),
|
||||
})
|
||||
|
||||
def test_pin_layout_oe(self):
|
||||
layout_1 = pin_layout(1, dir="oe", xdr=2)
|
||||
self.assertLayoutEqual(layout_1.fields, {
|
||||
"o_clk": (unsigned(1), DIR_NONE),
|
||||
"o0": (unsigned(1), DIR_NONE),
|
||||
"o1": (unsigned(1), DIR_NONE),
|
||||
"oe": (unsigned(1), DIR_NONE),
|
||||
def test_signature_oe(self):
|
||||
sig_1 = Pin.Signature(1, dir="oe", xdr=2)
|
||||
self.assertSignatureEqual(sig_1, {
|
||||
"o_clk": Out(1),
|
||||
"o0": Out(1),
|
||||
"o1": Out(1),
|
||||
"oe": Out(1),
|
||||
})
|
||||
|
||||
layout_2 = pin_layout(2, dir="oe", xdr=2)
|
||||
self.assertLayoutEqual(layout_2.fields, {
|
||||
"o_clk": (unsigned(1), DIR_NONE),
|
||||
"o0": (unsigned(2), DIR_NONE),
|
||||
"o1": (unsigned(2), DIR_NONE),
|
||||
"oe": (unsigned(1), DIR_NONE),
|
||||
sig_2 = Pin.Signature(2, dir="oe", xdr=2)
|
||||
self.assertSignatureEqual(sig_2, {
|
||||
"o_clk": Out(1),
|
||||
"o0": Out(2),
|
||||
"o1": Out(2),
|
||||
"oe": Out(1),
|
||||
})
|
||||
|
||||
def test_pin_layout_io(self):
|
||||
layout_1 = pin_layout(1, dir="io", xdr=2)
|
||||
self.assertLayoutEqual(layout_1.fields, {
|
||||
"i_clk": (unsigned(1), DIR_NONE),
|
||||
"i0": (unsigned(1), DIR_NONE),
|
||||
"i1": (unsigned(1), DIR_NONE),
|
||||
"o_clk": (unsigned(1), DIR_NONE),
|
||||
"o0": (unsigned(1), DIR_NONE),
|
||||
"o1": (unsigned(1), DIR_NONE),
|
||||
"oe": (unsigned(1), DIR_NONE),
|
||||
def test_signature_io(self):
|
||||
sig_1 = Pin.Signature(1, dir="io", xdr=2)
|
||||
self.assertSignatureEqual(sig_1, {
|
||||
"i_clk": Out(1),
|
||||
"i0": In(1),
|
||||
"i1": In(1),
|
||||
"o_clk": Out(1),
|
||||
"o0": Out(1),
|
||||
"o1": Out(1),
|
||||
"oe": Out(1),
|
||||
})
|
||||
|
||||
layout_2 = pin_layout(2, dir="io", xdr=2)
|
||||
self.assertLayoutEqual(layout_2.fields, {
|
||||
"i_clk": (unsigned(1), DIR_NONE),
|
||||
"i0": (unsigned(2), DIR_NONE),
|
||||
"i1": (unsigned(2), DIR_NONE),
|
||||
"o_clk": (unsigned(1), DIR_NONE),
|
||||
"o0": (unsigned(2), DIR_NONE),
|
||||
"o1": (unsigned(2), DIR_NONE),
|
||||
"oe": (unsigned(1), DIR_NONE),
|
||||
sig_2 = Pin.Signature(2, dir="io", xdr=2)
|
||||
self.assertSignatureEqual(sig_2, {
|
||||
"i_clk": Out(1),
|
||||
"i0": In(2),
|
||||
"i1": In(2),
|
||||
"o_clk": Out(1),
|
||||
"o0": Out(2),
|
||||
"o1": Out(2),
|
||||
"oe": Out(1),
|
||||
})
|
||||
|
||||
|
||||
|
|
@ -211,3 +205,7 @@ class PinTestCase(FHDLTestCase):
|
|||
self.assertEqual(pin.width, 2)
|
||||
self.assertEqual(pin.dir, "io")
|
||||
self.assertEqual(pin.xdr, 2)
|
||||
self.assertEqual(pin.signature.width, 2)
|
||||
self.assertEqual(pin.signature.dir, "io")
|
||||
self.assertEqual(pin.signature.xdr, 2)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue