*: remove unused variables

nmigen/hdl/rec.py

@@ -49,7 +49,7 @@ class Layout:
                 try:
                     # Check provided shape by calling Shape.cast and checking for exception
                     Shape.cast(shape, src_loc_at=1 + src_loc_at)
-                except Exception as error:
+                except Exception:
                     raise TypeError("Field {!r} has invalid shape: should be castable to Shape "
                                     "or a list of fields of a nested record"
                                     .format(field))

nmigen/lib/fifo.py

@@ -300,7 +300,7 @@ class AsyncFIFO(Elaboratable, FIFOInterface):
             try:
                 depth_bits = log2_int(depth, need_pow2=exact_depth)
                 depth = 1 << depth_bits
-            except ValueError as e:
+            except ValueError:
                 raise ValueError("AsyncFIFO only supports depths that are powers of 2; requested "
                                  "exact depth {} is not"
                                  .format(depth)) from None
@@ -480,7 +480,7 @@ class AsyncFIFOBuffered(Elaboratable, FIFOInterface):
             try:
                 depth_bits = log2_int(max(0, depth - 1), need_pow2=exact_depth)
                 depth = (1 << depth_bits) + 1
-            except ValueError as e:
+            except ValueError:
                 raise ValueError("AsyncFIFOBuffered only supports depths that are one higher "
                                  "than powers of 2; requested exact depth {} is not"
                                  .format(depth)) from None

nmigen/sim/_pyrtl.py

@@ -140,8 +140,6 @@ class _RHSValueCompiler(_ValueCompiler):
                 return self(arg)
         elif len(value.operands) == 2:
             lhs, rhs = value.operands
-            lhs_mask = (1 << len(lhs)) - 1
-            rhs_mask = (1 << len(rhs)) - 1
             if value.operator == "+":
                 return f"({sign(lhs)} + {sign(rhs)})"
             if value.operator == "-":
@@ -217,7 +215,6 @@ class _RHSValueCompiler(_ValueCompiler):
         gen_index = self.emitter.def_var("rhs_index", f"{index_mask} & {self(value.index)}")
         gen_value = self.emitter.gen_var("rhs_proxy")
         if value.elems:
-            gen_elems = []
             for index, elem in enumerate(value.elems):
                 if index == 0:
                     self.emitter.append(f"if {index} == {gen_index}:")
@@ -292,7 +289,6 @@ class _LHSValueCompiler(_ValueCompiler):
     def on_Cat(self, value):
         def gen(arg):
             gen_arg = self.emitter.def_var("cat", arg)
-            gen_parts = []
             offset = 0
             for part in value.parts:
                 part_mask = (1 << len(part)) - 1
@@ -308,7 +304,6 @@ class _LHSValueCompiler(_ValueCompiler):
             index_mask = (1 << len(value.index)) - 1
             gen_index = self.emitter.def_var("index", f"{self.rrhs(value.index)} & {index_mask}")
             if value.elems:
-                gen_elems = []
                 for index, elem in enumerate(value.elems):
                     if index == 0:
                         self.emitter.append(f"if {index} == {gen_index}:")